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authorH. Peter Anvin <hpa@zytor.com>2021-01-24 16:40:19 -0800
committerH. Peter Anvin <hpa@zytor.com>2021-01-24 16:40:19 -0800
commit6079da19e9086c427b1abd3dffd2a45262b5a014 (patch)
tree282c54eb6ac614d00fe27bb2186b37b225e51023
parent4814dff383fa0da31d3bcecd334b5929757b0abb (diff)
downloadabc80-1m-sram-6079da19e9086c427b1abd3dffd2a45262b5a014.tar.gz
abc80-1m-sram-6079da19e9086c427b1abd3dffd2a45262b5a014.tar.xz
abc80-1m-sram-6079da19e9086c427b1abd3dffd2a45262b5a014.zip
Starting v1.2: TKN80-friendly version of the board
-rw-r--r--v1.2/abc80-1m-sram.brd2957
-rw-r--r--v1.2/abc80-1m-sram.sch8315
-rw-r--r--v1.2/bom.xlsxbin0 -> 7649 bytes
l---------v1.2/cam/jlcpcb-2layer.cam1
-rw-r--r--v1.2/eagle.epf559
-rw-r--r--v1.2/pld/Makefile11
-rw-r--r--v1.2/pld/abc80-1m-ic4.absbin0 -> 5396 bytes
-rw-r--r--v1.2/pld/abc80-1m-ic4.doc395
-rw-r--r--v1.2/pld/abc80-1m-ic4.jed99
-rw-r--r--v1.2/pld/abc80-1m-ic4.mx106
-rw-r--r--v1.2/pld/abc80-1m-ic4.pdf225
-rw-r--r--v1.2/pld/abc80-1m-ic4.pla82
-rw-r--r--v1.2/pld/abc80-1m-ic4.pld106
-rw-r--r--v1.2/pld/abc80-1m-ic4.sim156
-rw-r--r--v1.2/pld/abc80-1m-ic5.absbin0 -> 3738 bytes
-rw-r--r--v1.2/pld/abc80-1m-ic5.doc331
-rw-r--r--v1.2/pld/abc80-1m-ic5.jed59
-rw-r--r--v1.2/pld/abc80-1m-ic5.mx122
-rw-r--r--v1.2/pld/abc80-1m-ic5.pdf222
-rw-r--r--v1.2/pld/abc80-1m-ic5.pla54
-rw-r--r--v1.2/pld/abc80-1m-ic5.pld122
-rw-r--r--v1.2/pld/abc80-1m-ic5.sim107
-rw-r--r--v1.2/pld/abc80-1m-ic9.absbin0 -> 1724 bytes
-rw-r--r--v1.2/pld/abc80-1m-ic9.doc180
-rw-r--r--v1.2/pld/abc80-1m-ic9.jed34
-rw-r--r--v1.2/pld/abc80-1m-ic9.mx59
-rw-r--r--v1.2/pld/abc80-1m-ic9.pdf187
-rw-r--r--v1.2/pld/abc80-1m-ic9.pla37
-rw-r--r--v1.2/pld/abc80-1m-ic9.pld59
-rw-r--r--v1.2/pld/abc80-1m-ic9.sim49
30 files changed, 14634 insertions, 0 deletions
diff --git a/v1.2/abc80-1m-sram.brd b/v1.2/abc80-1m-sram.brd
new file mode 100644
index 0000000..9f6e8cb
--- /dev/null
+++ b/v1.2/abc80-1m-sram.brd
@@ -0,0 +1,2957 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.7.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="yes"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.05" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.025" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
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+<layer number="101" name="Patch_Top" color="12" fill="4" visible="yes" active="yes"/>
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+<layer number="122" name="_bsilk" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="151" name="HeatSink" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="200" name="200bmp" color="1" fill="10" visible="no" active="no"/>
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+<layer number="251" name="SMDround" color="12" fill="11" visible="no" active="no"/>
+<layer number="254" name="cooling" color="7" fill="1" visible="yes" active="yes"/>
+</layers>
+<board>
+<plain>
+<wire x1="99.06" y1="0" x2="99.06" y2="78.74" width="0" layer="20"/>
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+<text x="0.635" y="22.86" size="1.27" layer="25" rot="R270" align="bottom-right">ABC80 1.5 MB SRAM/flash</text>
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+<text x="91.44" y="70.485" size="1.016" layer="25" ratio="12" rot="R270" align="center-left">(set jumper to correct type)</text>
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+<text x="72.39" y="57.15" size="1.016" layer="25" ratio="12" rot="R270" align="center-left">(no flash)</text>
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+<text x="0.635" y="57.785" size="1.016" layer="27" ratio="10" rot="R90" align="top-left">(C) 2020 H. Peter Anvin</text>
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+<text x="69.85" y="34.925" size="1.016" layer="27" ratio="12" rot="R180" align="center-left">IC2</text>
+<text x="97.79" y="35.56" size="1.016" layer="27" ratio="12" rot="R180">IC3</text>
+<wire x1="0" y1="0" x2="99.06" y2="0" width="0" layer="20"/>
+<text x="53.975" y="3.81" size="1.016" layer="25" ratio="10" rot="R90" align="center">Boot map</text>
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+</plain>
+<libraries>
+<library name="zilog">
+<description>&lt;b&gt;Zilog Z80 Microprocessor Devices&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
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+<description>&lt;b&gt;TTL Devices, 74xx Series with US Symbols&lt;/b&gt;&lt;p&gt;
+Based on the following sources:
+&lt;ul&gt;
+&lt;li&gt;Texas Instruments &lt;i&gt;TTL Data Book&lt;/i&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Volume 1, 1996.
+&lt;li&gt;TTL Data Book, Volume 2 , 1993
+&lt;li&gt;National Seminconductor Databook 1990, ALS/LS Logic
+&lt;li&gt;ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+&lt;li&gt;http://icmaster.com/ViewCompare.asp
+&lt;/ul&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
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+<pad name="10" x="11.43" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="11.43" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="-1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="17" x="-3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="18" x="-6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="19" x="-8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="20" x="-11.43" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<text x="-13.081" y="-3.048" size="1.27" layer="25" rot="R90">&gt;NAME</text>
+<text x="-9.779" y="-0.381" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+<package name="DIL14">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt;</description>
+<wire x1="8.89" y1="2.921" x2="-8.89" y2="2.921" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="-2.921" x2="8.89" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="8.89" y1="2.921" x2="8.89" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="2.921" x2="-8.89" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="-2.921" x2="-8.89" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-8.89" y1="1.016" x2="-8.89" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
+<pad name="1" x="-7.62" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-5.08" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="7.62" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="7.62" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-2.54" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="0" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="5.08" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="2.54" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="5.08" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="2.54" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="0" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="-2.54" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="-5.08" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="-7.62" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<text x="-9.271" y="-3.048" size="1.27" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-6.731" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="memory-bsi">
+<description>BSI sram memory modules
+
+BS64LV4006 and BS64LV256
+
+luc@tan.nu</description>
+<packages>
+<package name="DIL-32">
+<wire x1="20.32" y1="6.731" x2="-20.32" y2="6.731" width="0.1524" layer="21"/>
+<wire x1="-20.32" y1="-6.731" x2="20.32" y2="-6.731" width="0.1524" layer="21"/>
+<wire x1="20.32" y1="6.731" x2="20.32" y2="-6.731" width="0.1524" layer="21"/>
+<wire x1="-20.32" y1="6.731" x2="-20.32" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-20.32" y1="-6.731" x2="-20.32" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-20.32" y1="1.016" x2="-20.32" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
+<pad name="1" x="-19.05" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="-3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="-1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="-6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="-8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="19.05" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="17" x="19.05" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="18" x="16.51" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="19" x="13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="20" x="11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="21" x="8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="22" x="6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="23" x="3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="24" x="1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="25" x="-1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="26" x="-3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="27" x="-6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="28" x="-8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="29" x="-11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="30" x="-13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="31" x="-16.51" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="32" x="-19.05" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<text x="-20.701" y="-6.604" size="1.778" layer="25" rot="R90">&gt;NAME</text>
+<text x="-16.891" y="-0.889" size="1.778" layer="27">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="74xx-eu">
+<description>&lt;b&gt;TTL Devices, 74xx Series with European Symbols&lt;/b&gt;&lt;p&gt;
+Based on the following sources:
+&lt;ul&gt;
+&lt;li&gt;Texas Instruments &lt;i&gt;TTL Data Book&lt;/i&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Volume 1, 1996.
+&lt;li&gt;TTL Data Book, Volume 2 , 1993
+&lt;li&gt;National Seminconductor Databook 1990, ALS/LS Logic
+&lt;li&gt;ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+&lt;li&gt;http://icmaster.com/ViewCompare.asp
+&lt;/ul&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL16">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt;</description>
+<wire x1="10.16" y1="2.921" x2="-10.16" y2="2.921" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="-2.921" x2="10.16" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="10.16" y1="2.921" x2="10.16" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="2.921" x2="-10.16" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="-2.921" x2="-10.16" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="1.016" x2="-10.16" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
+<pad name="1" x="-8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="-1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="-3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="-6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="-8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<text x="-10.541" y="-2.921" size="1.27" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-7.493" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="DIL20">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt;</description>
+<wire x1="12.7" y1="2.921" x2="-12.7" y2="2.921" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="-2.921" x2="12.7" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="12.7" y1="2.921" x2="12.7" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="2.921" x2="-12.7" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="-2.921" x2="-12.7" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="1.016" x2="-12.7" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
+<pad name="1" x="-11.43" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="-1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="11.43" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="11.43" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="-1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="17" x="-3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="18" x="-6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="19" x="-8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="20" x="-11.43" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<text x="-13.081" y="-3.048" size="1.27" layer="25" rot="R90">&gt;NAME</text>
+<text x="-9.779" y="-0.381" size="1.27" layer="27">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="con-lstb">
+<description>&lt;b&gt;Pin Headers&lt;/b&gt;&lt;p&gt;
+Naming:&lt;p&gt;
+MA = male&lt;p&gt;
+# contacts - # rows&lt;p&gt;
+W = angled&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="MA20-1">
+<description>&lt;b&gt;PIN HEADER&lt;/b&gt;</description>
+<wire x1="-24.765" y1="1.27" x2="-23.495" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-23.495" y1="1.27" x2="-22.86" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-22.86" y1="-0.635" x2="-23.495" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-22.86" y1="0.635" x2="-22.225" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-22.225" y1="1.27" x2="-20.955" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-20.955" y1="1.27" x2="-20.32" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-20.32" y1="-0.635" x2="-20.955" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-20.955" y1="-1.27" x2="-22.225" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-22.225" y1="-1.27" x2="-22.86" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-25.4" y1="0.635" x2="-25.4" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-24.765" y1="1.27" x2="-25.4" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-25.4" y1="-0.635" x2="-24.765" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-23.495" y1="-1.27" x2="-24.765" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-20.32" y1="0.635" x2="-19.685" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-19.685" y1="1.27" x2="-18.415" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-18.415" y1="1.27" x2="-17.78" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-17.78" y1="-0.635" x2="-18.415" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-18.415" y1="-1.27" x2="-19.685" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-19.685" y1="-1.27" x2="-20.32" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-17.145" y1="1.27" x2="-15.875" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-15.875" y1="1.27" x2="-15.24" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-15.24" y1="-0.635" x2="-15.875" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-15.24" y1="0.635" x2="-14.605" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-14.605" y1="1.27" x2="-13.335" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-13.335" y1="1.27" x2="-12.7" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="-0.635" x2="-13.335" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-13.335" y1="-1.27" x2="-14.605" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-14.605" y1="-1.27" x2="-15.24" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-17.145" y1="1.27" x2="-17.78" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-17.78" y1="-0.635" x2="-17.145" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-15.875" y1="-1.27" x2="-17.145" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="1.27" x2="1.905" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="1.905" y1="1.27" x2="2.54" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-0.635" x2="1.905" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.635" x2="3.175" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="1.27" x2="4.445" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="1.27" x2="5.08" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="-0.635" x2="4.445" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="-1.27" x2="3.175" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="-1.27" x2="2.54" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="1.27" x2="0" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="-0.635" x2="0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="1.905" y1="-1.27" x2="0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="0.635" x2="5.715" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="5.715" y1="1.27" x2="6.985" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="6.985" y1="1.27" x2="7.62" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="7.62" y1="-0.635" x2="6.985" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="6.985" y1="-1.27" x2="5.715" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="5.715" y1="-1.27" x2="5.08" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="8.255" y1="1.27" x2="9.525" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="9.525" y1="1.27" x2="10.16" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="10.16" y1="-0.635" x2="9.525" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="10.16" y1="0.635" x2="10.795" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="10.795" y1="1.27" x2="12.065" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="12.065" y1="1.27" x2="12.7" y2="0.635" width="0.1524" layer="21"/>
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+<wire x1="18.415" y1="1.27" x2="19.685" y2="1.27" width="0.1524" layer="21"/>
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+<wire x1="18.415" y1="-1.27" x2="17.78" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="20.955" y1="1.27" x2="22.225" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="22.225" y1="1.27" x2="22.86" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="22.86" y1="-0.635" x2="22.225" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="22.86" y1="0.635" x2="23.495" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="23.495" y1="1.27" x2="24.765" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="24.765" y1="1.27" x2="25.4" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="25.4" y1="0.635" x2="25.4" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="25.4" y1="-0.635" x2="24.765" y2="-1.27" width="0.1524" layer="21"/>
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+<wire x1="22.225" y1="-1.27" x2="20.955" y2="-1.27" width="0.1524" layer="21"/>
+<pad name="1" x="-24.13" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="2" x="-21.59" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="3" x="-19.05" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="4" x="-16.51" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="5" x="-13.97" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="6" x="-11.43" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="7" x="-8.89" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="8" x="-6.35" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="9" x="-3.81" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="10" x="-1.27" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="11" x="1.27" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="12" x="3.81" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="13" x="6.35" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="14" x="8.89" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="15" x="11.43" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="16" x="13.97" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="17" x="16.51" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="18" x="19.05" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="19" x="21.59" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="20" x="24.13" y="0" drill="1.016" shape="long" rot="R90"/>
+<text x="-25.4" y="1.651" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-24.384" y="-2.794" size="1.27" layer="21" ratio="10">1</text>
+<text x="23.241" y="-2.921" size="1.27" layer="21" ratio="10">20</text>
+<text x="-1.905" y="-2.921" size="1.27" layer="21" ratio="10">10</text>
+<text x="-17.78" y="1.651" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
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+<rectangle x1="-14.3002" y1="-0.3302" x2="-13.6398" y2="0.3302" layer="51"/>
+<rectangle x1="3.4798" y1="-0.3302" x2="4.1402" y2="0.3302" layer="51"/>
+<rectangle x1="6.0198" y1="-0.3302" x2="6.6802" y2="0.3302" layer="51"/>
+<rectangle x1="8.5598" y1="-0.3302" x2="9.2202" y2="0.3302" layer="51"/>
+<rectangle x1="11.0998" y1="-0.3302" x2="11.7602" y2="0.3302" layer="51"/>
+<rectangle x1="-11.7602" y1="-0.3302" x2="-11.0998" y2="0.3302" layer="51"/>
+<rectangle x1="-9.2202" y1="-0.3302" x2="-8.5598" y2="0.3302" layer="51"/>
+<rectangle x1="-6.6802" y1="-0.3302" x2="-6.0198" y2="0.3302" layer="51"/>
+<rectangle x1="-4.1402" y1="-0.3302" x2="-3.4798" y2="0.3302" layer="51"/>
+<rectangle x1="-1.6002" y1="-0.3302" x2="-0.9398" y2="0.3302" layer="51"/>
+<rectangle x1="13.6398" y1="-0.3302" x2="14.3002" y2="0.3302" layer="51"/>
+<rectangle x1="16.1798" y1="-0.3302" x2="16.8402" y2="0.3302" layer="51"/>
+<rectangle x1="18.7198" y1="-0.3302" x2="19.3802" y2="0.3302" layer="51"/>
+<rectangle x1="21.2598" y1="-0.3302" x2="21.9202" y2="0.3302" layer="51"/>
+<rectangle x1="23.7998" y1="-0.3302" x2="24.4602" y2="0.3302" layer="51"/>
+</package>
+</packages>
+</library>
+<library name="pal">
+<description>&lt;b&gt;PALs&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL24-3">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt; 0.3 inch</description>
+<wire x1="-14.986" y1="-0.635" x2="-14.986" y2="-2.794" width="0.1524" layer="21"/>
+<wire x1="-14.986" y1="0.635" x2="-14.986" y2="-0.635" width="0.1524" layer="21" curve="-180"/>
+<wire x1="14.986" y1="-2.794" x2="14.986" y2="2.794" width="0.1524" layer="21"/>
+<wire x1="-14.986" y1="-2.794" x2="14.986" y2="-2.794" width="0.1524" layer="21"/>
+<wire x1="-14.986" y1="2.794" x2="14.986" y2="2.794" width="0.1524" layer="21"/>
+<wire x1="-14.986" y1="2.794" x2="-14.986" y2="0.635" width="0.1524" layer="21"/>
+<pad name="1" x="-13.97" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-11.43" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="-3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="-1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="11.43" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="13.97" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="13.97" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="11.43" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="17" x="3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="18" x="1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="19" x="-1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="20" x="-3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="21" x="-6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="22" x="-8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="23" x="-11.43" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="24" x="-13.97" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<text x="-15.2908" y="-2.667" size="1.778" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-13.462" y="-0.889" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="rcl">
+<description>&lt;b&gt;Resistors, Capacitors, Inductors&lt;/b&gt;&lt;p&gt;
+Based on the previous libraries:
+&lt;ul&gt;
+&lt;li&gt;r.lbr
+&lt;li&gt;cap.lbr
+&lt;li&gt;cap-fe.lbr
+&lt;li&gt;captant.lbr
+&lt;li&gt;polcap.lbr
+&lt;li&gt;ipc-smd.lbr
+&lt;/ul&gt;
+All SMD packages are defined according to the IPC specifications and CECC&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;&lt;p&gt;
+&lt;p&gt;
+for Electrolyt Capacitors see also :&lt;p&gt;
+www.bccomponents.com &lt;p&gt;
+www.panasonic.com&lt;p&gt;
+www.kemet.com&lt;p&gt;
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf &lt;b&gt;(SANYO)&lt;/b&gt;
+&lt;p&gt;
+for trimmer refence see : &lt;u&gt;www.electrospec-inc.com/cross_references/trimpotcrossref.asp&lt;/u&gt;&lt;p&gt;
+
+&lt;table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0&gt;
+&lt;tr valign="top"&gt;
+
+&lt;! &lt;td width="10"&gt;&amp;nbsp;&lt;/td&gt;
+&lt;td width="90%"&gt;
+
+&lt;b&gt;&lt;font color="#0000FF" size="4"&gt;TRIM-POT CROSS REFERENCE&lt;/font&gt;&lt;/b&gt;
+&lt;P&gt;
+&lt;TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2&gt;
+ &lt;TR&gt;
+ &lt;TD COLSPAN=8&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;RECTANGULAR MULTI-TURN&lt;/B&gt;&lt;/FONT&gt;
+ &lt;/TD&gt;
+ &lt;/TR&gt;
+ &lt;TR&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;BOURNS&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;BI&amp;nbsp;TECH&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;DALE-VISHAY&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;PHILIPS/MEPCO&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;MURATA&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;PANASONIC&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;SPECTROL&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;MILSPEC&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;&lt;TD&gt;&amp;nbsp;&lt;/TD&gt;
+ &lt;/TR&gt;
+ &lt;TR&gt;
+ &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3 &gt;
+ 3005P&lt;BR&gt;
+ 3006P&lt;BR&gt;
+ 3006W&lt;BR&gt;
+ 3006Y&lt;BR&gt;
+ 3009P&lt;BR&gt;
+ 3009W&lt;BR&gt;
+ 3009Y&lt;BR&gt;
+ 3057J&lt;BR&gt;
+ 3057L&lt;BR&gt;
+ 3057P&lt;BR&gt;
+ 3057Y&lt;BR&gt;
+ 3059J&lt;BR&gt;
+ 3059L&lt;BR&gt;
+ 3059P&lt;BR&gt;
+ 3059Y&lt;BR&gt;&lt;/FONT&gt;
+ &lt;/TD&gt;
+ &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+ -&lt;BR&gt;
+ 89P&lt;BR&gt;
+ 89W&lt;BR&gt;
+ 89X&lt;BR&gt;
+ 89PH&lt;BR&gt;
+ 76P&lt;BR&gt;
+ 89XH&lt;BR&gt;
+ 78SLT&lt;BR&gt;
+ 78L&amp;nbsp;ALT&lt;BR&gt;
+ 56P&amp;nbsp;ALT&lt;BR&gt;
+ 78P&amp;nbsp;ALT&lt;BR&gt;
+ T8S&lt;BR&gt;
+ 78L&lt;BR&gt;
+ 56P&lt;BR&gt;
+ 78P&lt;BR&gt;&lt;/FONT&gt;
+ &lt;/TD&gt;
+ &lt;TD BGCOLOR="#cccccc" ALIGN=CENTER&gt;&lt;FONT FACE=ARIAL SIZE=3&gt;
+ -&lt;BR&gt;
+ T18/784&lt;BR&gt;
+ 783&lt;BR&gt;
+ 781&lt;BR&gt;
+ -&lt;BR&gt;
+ -&lt;BR&gt;
+ -&lt;BR&gt;
+ 2199&lt;BR&gt;
+ 1697/1897&lt;BR&gt;
+ 1680/1880&lt;BR&gt;
+ 2187&lt;BR&gt;
+ -&lt;BR&gt;
+ -&lt;BR&gt;
+ -&lt;BR&gt;
+ -&lt;BR&gt;&lt;/FONT&gt;
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+&lt;/TABLE&gt;
+&lt;P&gt;&amp;nbsp;&lt;P&gt;
+&lt;TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3&gt;
+ &lt;TR&gt;
+ &lt;TD COLSPAN=7&gt;
+ &lt;FONT color="#0000FF" SIZE=4 FACE=ARIAL&gt;&lt;B&gt;SMD TRIM-POT CROSS REFERENCE&lt;/B&gt;&lt;/FONT&gt;
+ &lt;P&gt;
+ &lt;FONT SIZE=4 FACE=ARIAL&gt;&lt;B&gt;MULTI-TURN&lt;/B&gt;&lt;/FONT&gt;
+ &lt;/TD&gt;
+ &lt;/TR&gt;
+ &lt;TR&gt;
+ &lt;TD&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BOURNS&lt;/B&gt;&lt;/FONT&gt;
+ &lt;/TD&gt;
+ &lt;TD&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BI&amp;nbsp;TECH&lt;/B&gt;&lt;/FONT&gt;
+ &lt;/TD&gt;
+ &lt;TD&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;DALE-VISHAY&lt;/B&gt;&lt;/FONT&gt;
+ &lt;/TD&gt;
+ &lt;TD&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PHILIPS/MEPCO&lt;/B&gt;&lt;/FONT&gt;
+ &lt;/TD&gt;
+ &lt;TD&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PANASONIC&lt;/B&gt;&lt;/FONT&gt;
+ &lt;/TD&gt;
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+ &lt;/TD&gt;
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+ &lt;/TD&gt;
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+ &lt;TR&gt;
+ &lt;TD COLSPAN=7&gt;&amp;nbsp;
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+ &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;BOURNS&lt;/B&gt;&lt;/FONT&gt;
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+ &lt;/TD&gt;
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+ &lt;/TD&gt;
+ &lt;TD&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;PHILIPS/MEPCO&lt;/B&gt;&lt;/FONT&gt;
+ &lt;/TD&gt;
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+ &lt;/TD&gt;
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+ &lt;/TD&gt;
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+ EVM-1E&lt;BR&gt;
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+ DVR-43A&lt;BR&gt;
+ CVR-42C&lt;BR&gt;
+ CVR-42A/C&lt;BR&gt;
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+&lt;P&gt;
+&lt;FONT SIZE=4 FACE=ARIAL&gt;&lt;B&gt;ALT =&amp;nbsp;ALTERNATE&lt;/B&gt;&lt;/FONT&gt;
+&lt;P&gt;
+
+&amp;nbsp;
+&lt;P&gt;
+&lt;/td&gt;
+&lt;/tr&gt;
+&lt;/table&gt;</description>
+<packages>
+<package name="C025-025X050">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+grid 2.5 mm, outline 2.5 x 5 mm</description>
+<wire x1="-2.159" y1="1.27" x2="2.159" y2="1.27" width="0.1524" layer="21"/>
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+<text x="-2.286" y="-2.794" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="switch">
+<description>&lt;b&gt;Switches&lt;/b&gt;&lt;p&gt;
+Marquardt, Siemens, C&amp;K, ITT, and others&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="TL3XPO">
+<description>&lt;b&gt;TINY SWITCH&lt;/b&gt;&lt;p&gt;
+Source: http://www2.produktinfo.conrad.com/datenblaetter/700000-724999/705152-da-01-de-Subminiaturschalter_TL_36YO.pdf</description>
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+</packages>
+</library>
+<library name="atmel">
+<description>&lt;b&gt;AVR Devices&lt;/b&gt;&lt;p&gt;
+Configurable logic, microcontrollers, nonvolatile memories&lt;p&gt;
+Based on the following sources:&lt;p&gt;
+&lt;ul&gt;
+&lt;li&gt;www.atmel.com
+&lt;li&gt;CD-ROM : Configurable Logic Microcontroller Nonvolatile Memory
+&lt;li&gt;CadSoft download site, www.cadsoft.de or www.cadsoftusa.com , file at90smcu_v400.zip
+&lt;li&gt;avr.lbr
+&lt;/ul&gt;
+&lt;author&gt;Revised by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
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+<pad name="20" x="-11.43" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<text x="-13.5128" y="-2.54" size="1.778" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-10.16" y="-0.762" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+</packages>
+</library>
+<library name="pinhead">
+<description>&lt;b&gt;Pin Header Connectors&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="1X06">
+<description>&lt;b&gt;PIN HEADER&lt;/b&gt;</description>
+<wire x1="0.635" y1="1.27" x2="1.905" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="1.905" y1="1.27" x2="2.54" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.635" x2="2.54" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="-0.635" x2="1.905" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="2.54" y1="0.635" x2="3.175" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="1.27" x2="4.445" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="1.27" x2="5.08" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="0.635" x2="5.08" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="-0.635" x2="4.445" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="4.445" y1="-1.27" x2="3.175" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="3.175" y1="-1.27" x2="2.54" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.635" x2="-1.905" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-1.905" y1="1.27" x2="-0.635" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="1.27" x2="0" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="0.635" x2="0" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="-0.635" x2="-0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="-1.27" x2="-1.905" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-1.905" y1="-1.27" x2="-2.54" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="0.635" y1="1.27" x2="0" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="-0.635" x2="0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="1.905" y1="-1.27" x2="0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-6.985" y1="1.27" x2="-5.715" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-5.715" y1="1.27" x2="-5.08" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0.635" x2="-5.08" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-0.635" x2="-5.715" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0.635" x2="-4.445" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="1.27" x2="-3.175" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="1.27" x2="-2.54" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="0.635" x2="-2.54" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-2.54" y1="-0.635" x2="-3.175" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="-1.27" x2="-4.445" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="-1.27" x2="-5.08" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-7.62" y1="0.635" x2="-7.62" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-6.985" y1="1.27" x2="-7.62" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-7.62" y1="-0.635" x2="-6.985" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-5.715" y1="-1.27" x2="-6.985" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="5.715" y1="1.27" x2="6.985" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="6.985" y1="1.27" x2="7.62" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="7.62" y1="0.635" x2="7.62" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="7.62" y1="-0.635" x2="6.985" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="5.715" y1="1.27" x2="5.08" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="5.08" y1="-0.635" x2="5.715" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="6.985" y1="-1.27" x2="5.715" y2="-1.27" width="0.1524" layer="21"/>
+<pad name="1" x="-6.35" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="2" x="-3.81" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="3" x="-1.27" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="4" x="1.27" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="5" x="3.81" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="6" x="6.35" y="0" drill="1.016" shape="long" rot="R90"/>
+<text x="-7.6962" y="1.8288" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-7.62" y="-3.175" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="3.556" y1="-0.254" x2="4.064" y2="0.254" layer="51"/>
+<rectangle x1="1.016" y1="-0.254" x2="1.524" y2="0.254" layer="51"/>
+<rectangle x1="-1.524" y1="-0.254" x2="-1.016" y2="0.254" layer="51"/>
+<rectangle x1="-4.064" y1="-0.254" x2="-3.556" y2="0.254" layer="51"/>
+<rectangle x1="-6.604" y1="-0.254" x2="-6.096" y2="0.254" layer="51"/>
+<rectangle x1="6.096" y1="-0.254" x2="6.604" y2="0.254" layer="51"/>
+</package>
+<package name="1X01/90">
+<description>&lt;b&gt;PIN HEADER&lt;/b&gt;</description>
+<wire x1="-1.27" y1="-1.905" x2="1.27" y2="-1.905" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="-1.905" x2="1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="1.27" y1="0.635" x2="-1.27" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-1.27" y1="0.635" x2="-1.27" y2="-1.905" width="0.1524" layer="21"/>
+<wire x1="0" y1="6.985" x2="0" y2="1.27" width="0.762" layer="21"/>
+<pad name="1" x="0" y="-3.81" drill="1.016" shape="long" rot="R90"/>
+<text x="-1.905" y="-3.81" size="1.27" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="3.175" y="-3.81" size="1.27" layer="27" rot="R90">&gt;VALUE</text>
+<rectangle x1="-0.381" y1="0.635" x2="0.381" y2="1.143" layer="21"/>
+<rectangle x1="-0.381" y1="-2.921" x2="0.381" y2="-1.905" layer="21"/>
+</package>
+</packages>
+</library>
+<library name="transistors">
+<packages>
+<package name="TO-92">
+<wire x1="-2.0946" y1="-1.651" x2="-0.7863" y2="2.5485" width="0.1524" layer="21" curve="-111.098957" cap="flat"/>
+<wire x1="0.7863" y1="2.5484" x2="2.0945" y2="-1.651" width="0.1524" layer="21" curve="-111.09954" cap="flat"/>
+<wire x1="-2.0945" y1="-1.651" x2="2.0945" y2="-1.651" width="0.1524" layer="21"/>
+<wire x1="-2.2537" y1="-0.254" x2="-0.2863" y2="-0.254" width="0.1524" layer="27"/>
+<wire x1="-2.6549" y1="-0.254" x2="-2.2537" y2="-0.254" width="0.1524" layer="21"/>
+<wire x1="-0.2863" y1="-0.254" x2="0.2863" y2="-0.254" width="0.1524" layer="21"/>
+<wire x1="2.2537" y1="-0.254" x2="2.6549" y2="-0.254" width="0.1524" layer="21"/>
+<wire x1="0.2863" y1="-0.254" x2="2.2537" y2="-0.254" width="0.1524" layer="27"/>
+<wire x1="-0.7863" y1="2.5485" x2="0.7863" y2="2.5485" width="0.1524" layer="27" curve="-34.293591" cap="flat"/>
+<pad name="3" x="1.27" y="0" drill="0.8128" shape="octagon"/>
+<pad name="2" x="0" y="1.905" drill="0.8128" shape="octagon"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="3.175" y="0.635" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="3.175" y="-1.27" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<text x="-0.635" y="0.635" size="1.27" layer="27" ratio="10">2</text>
+<text x="-2.159" y="0" size="1.27" layer="27" ratio="10">1</text>
+<text x="1.143" y="0" size="1.27" layer="27" ratio="10">3</text>
+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0.2032" drill="0">
+</class>
+<class number="1" name="supply" width="0.8128" drill="0">
+</class>
+</classes>
+<designrules name="default">
+<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+Die Standard-Design-Rules sind so gewählt, dass sie für
+die meisten Anwendungen passen. Sollte ihre Platine
+besondere Anforderungen haben, treffen Sie die erforderlichen
+Einstellungen hier und speichern die Design Rules unter
+einem neuen Namen ab.</description>
+<description language="en">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+The default Design Rules have been set to cover
+a wide range of applications. Your particular design
+may have different requirements, so please make the
+necessary adjustments and save your customized
+design rules under a new name.</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>
+<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>
+<param name="mdWireWire" value="8mil"/>
+<param name="mdWirePad" value="8mil"/>
+<param name="mdWireVia" value="8mil"/>
+<param name="mdPadPad" value="8mil"/>
+<param name="mdPadVia" value="8mil"/>
+<param name="mdViaVia" value="8mil"/>
+<param name="mdSmdPad" value="8mil"/>
+<param name="mdSmdVia" value="8mil"/>
+<param name="mdSmdSmd" value="8mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="40mil"/>
+<param name="mdDrill" value="8mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="10mil"/>
+<param name="msDrill" value="24mil"/>
+<param name="msMicroVia" value="9.99mm"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="10mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="10mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="10mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="8mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="8mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="4mil"/>
+<param name="mlMaxStopFrame" value="4mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="0mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="10mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="25mil"/>
+<param name="AutoGrid" value="1"/>
+<param name="Efforts" value="2"/>
+<param name="TopRouterVariant" value="1"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="a"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="a"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+<param name="cfExtdStep" value="10"/>
+<param name="cfHugging" value="1"/>
+<param name="mnExtdSteps" value="1"/>
+<param name="mnRipupLevel" value="0"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+<param name="cfNonPref" value="0"/>
+<param name="cfChangeDir" value="6"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="2"/>
+<param name="cfMalusStep" value="2"/>
+<param name="cfPadImpact" value="2"/>
+<param name="cfSmdImpact" value="2"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfChangeDir" value="8"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+</pass>
+<pass name="Optimize4" refer="Optimize3" active="yes">
+<param name="cfChangeDir" value="25"/>
+</pass>
+</autorouter>
+<elements>
+<element name="CPU" library="zilog" package="DIL40" value="Z80CPU" x="11.43" y="50.8" smashed="yes" rot="R270">
+<attribute name="NAME" x="8.001" y="76.708" size="1.778" layer="25"/>
+<attribute name="VALUE" x="10.414" y="67.945" size="1.778" layer="27" rot="R270"/>
+</element>
+<element name="IC1" library="memory-bsi" package="DIL-32" value="512Kx8 SRAM" x="50.8" y="57.15" smashed="yes" rot="R90">
+<attribute name="NAME" x="52.07" y="40.64" size="1.778" layer="25" ratio="12" rot="SR90"/>
+<attribute name="VALUE" x="50.419" y="45.974" size="1.778" layer="27" ratio="12" rot="R90"/>
+</element>
+<element name="IC10" library="74xx-us" package="DIL20" value="74HCT245N" x="33.02" y="33.02" smashed="yes" rot="R270">
+<attribute name="NAME" x="26.924" y="40.767" size="1.27" layer="25" ratio="10" rot="R90"/>
+<attribute name="VALUE" x="33.909" y="36.449" size="1.27" layer="27" ratio="10" rot="R270"/>
+</element>
+<element name="IC8" library="74xx-eu" package="DIL16" value="74HCT157N" x="60.96" y="17.78" smashed="yes" rot="R270">
+<attribute name="NAME" x="59.309" y="6.096" size="1.27" layer="25" ratio="10"/>
+<attribute name="VALUE" x="60.325" y="25.273" size="1.27" layer="27" ratio="10" rot="R270"/>
+</element>
+<element name="J3A" library="con-lstb" package="MA20-1" value="" x="7.62" y="50.8" rot="MR270">
+<attribute name="MPN" value="" x="7.62" y="50.8" size="1.778" layer="28" rot="MR270" display="off"/>
+<attribute name="OC_FARNELL" value="unknown" x="7.62" y="50.8" size="1.778" layer="28" rot="MR270" display="off"/>
+<attribute name="MF" value="" x="7.62" y="50.8" size="1.778" layer="28" rot="MR270" display="off"/>
+<attribute name="OC_NEWARK" value="unknown" x="7.62" y="50.8" size="1.778" layer="28" rot="MR270" display="off"/>
+</element>
+<element name="J3B" library="con-lstb" package="MA20-1" value="" x="22.86" y="50.8" rot="MR90">
+<attribute name="MPN" value="" x="22.86" y="50.8" size="1.778" layer="28" rot="MR90" display="off"/>
+<attribute name="OC_FARNELL" value="unknown" x="22.86" y="50.8" size="1.778" layer="28" rot="MR90" display="off"/>
+<attribute name="MF" value="" x="22.86" y="50.8" size="1.778" layer="28" rot="MR90" display="off"/>
+<attribute name="OC_NEWARK" value="unknown" x="22.86" y="50.8" size="1.778" layer="28" rot="MR90" display="off"/>
+</element>
+<element name="IC3" library="memory-bsi" package="DIL-32" value="512Kx8 SRAM/flash" x="88.9" y="57.15" smashed="yes" rot="R90">
+<attribute name="NAME" x="90.17" y="41.275" size="1.778" layer="25" ratio="12" rot="SR90"/>
+<attribute name="VALUE" x="88.519" y="46.609" size="1.778" layer="27" ratio="12" rot="R90"/>
+</element>
+<element name="IC4" library="pal" package="DIL24-3" value="22V10-IC4" x="45.72" y="16.51" smashed="yes" rot="R270">
+<attribute name="MPN" value="GAL22V10D-7LPN" x="45.72" y="16.51" size="1.778" layer="27" rot="R270" display="off"/>
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+<wire x1="91.44" y1="15.24" x2="91.44" y2="19.05" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="MD1">
+<contactref element="IC1" pad="14"/>
+<contactref element="IC3" pad="14"/>
+<contactref element="IC2" pad="14"/>
+<contactref element="IC10" pad="11"/>
+<contactref element="IC7" pad="14"/>
+<contactref element="IC6" pad="4"/>
+<contactref element="IC9" pad="12"/>
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+<wire x1="88.9" y1="15.24" x2="81.28" y2="19.05" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="MD2">
+<contactref element="IC1" pad="15"/>
+<contactref element="IC3" pad="15"/>
+<contactref element="IC2" pad="15"/>
+<contactref element="IC10" pad="14"/>
+<contactref element="IC7" pad="17"/>
+<contactref element="IC6" pad="7"/>
+<contactref element="IC9" pad="13"/>
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+<wire x1="88.9" y1="19.05" x2="81.28" y2="15.24" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="MD3">
+<contactref element="IC1" pad="17"/>
+<contactref element="IC3" pad="17"/>
+<contactref element="IC2" pad="17"/>
+<contactref element="IC6" pad="14"/>
+<contactref element="IC10" pad="17"/>
+<contactref element="IC7" pad="18"/>
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+<wire x1="88.9" y1="26.67" x2="78.74" y2="15.24" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="MD4">
+<contactref element="IC1" pad="18"/>
+<contactref element="IC3" pad="18"/>
+<contactref element="IC2" pad="18"/>
+<contactref element="IC6" pad="17"/>
+<contactref element="IC10" pad="18"/>
+<contactref element="IC5" pad="11"/>
+<wire x1="62.23" y1="73.66" x2="81.28" y2="73.66" width="0" layer="19" extent="1-1"/>
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+<wire x1="81.28" y1="26.67" x2="36.83" y2="39.37" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="MD5">
+<contactref element="IC1" pad="19"/>
+<contactref element="IC3" pad="19"/>
+<contactref element="IC2" pad="19"/>
+<contactref element="IC6" pad="18"/>
+<contactref element="IC10" pad="16"/>
+<contactref element="IC7" pad="4"/>
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+<wire x1="81.28" y1="7.62" x2="78.74" y2="26.67" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="MD6">
+<contactref element="IC1" pad="20"/>
+<contactref element="IC3" pad="20"/>
+<contactref element="IC2" pad="20"/>
+<contactref element="IC4" pad="13"/>
+<contactref element="IC10" pad="15"/>
+<contactref element="IC5" pad="9"/>
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+<wire x1="49.53" y1="2.54" x2="22.86" y2="3.81" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="MD7">
+<contactref element="IC1" pad="21"/>
+<contactref element="IC3" pad="21"/>
+<contactref element="IC2" pad="21"/>
+<contactref element="IC10" pad="13"/>
+<contactref element="IC5" pad="13"/>
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+<wire x1="62.23" y1="66.04" x2="81.28" y2="66.04" width="0" layer="19" extent="1-1"/>
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+<wire x1="41.91" y1="5.08" x2="30.48" y2="11.43" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="!ACLR">
+<contactref element="IC6" pad="1"/>
+<contactref element="IC11" pad="4"/>
+<wire x1="16.51" y1="15.24" x2="73.66" y2="19.05" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="MAP1">
+<contactref element="IC7" pad="15"/>
+<contactref element="IC8" pad="6"/>
+<wire x1="57.15" y1="13.97" x2="86.36" y2="15.24" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="MAP3">
+<contactref element="IC7" pad="19"/>
+<contactref element="IC8" pad="10"/>
+<wire x1="64.77" y1="11.43" x2="76.2" y2="15.24" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="!BYPASS">
+<contactref element="IC5" pad="16"/>
+<contactref element="IC4" pad="9"/>
+<contactref element="IC9" pad="7"/>
+<wire x1="22.86" y1="11.43" x2="29.21" y2="58.42" width="0" layer="19" extent="1-1"/>
+<wire x1="41.91" y1="10.16" x2="22.86" y2="11.43" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="MUXA">
+<contactref element="IC6" pad="11"/>
+<contactref element="IC9" pad="8"/>
+<contactref element="IC11" pad="10"/>
+<wire x1="29.21" y1="55.88" x2="96.52" y2="26.67" width="0" layer="19" extent="1-1"/>
+<wire x1="19.05" y1="22.86" x2="29.21" y2="55.88" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="!CS0">
+<contactref element="IC1" pad="22"/>
+<contactref element="IC4" pad="18"/>
+<wire x1="49.53" y1="15.24" x2="43.18" y2="63.5" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="!CS1">
+<contactref element="IC2" pad="22"/>
+<contactref element="IC4" pad="19"/>
+<wire x1="49.53" y1="17.78" x2="62.23" y2="63.5" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="A13_SYS">
+<contactref element="J3A" pad="3"/>
+<contactref element="IC9" pad="19"/>
+<wire x1="7.62" y1="69.85" x2="36.83" y2="71.12" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="A14_SYS">
+<contactref element="J3A" pad="4"/>
+<contactref element="IC9" pad="18"/>
+<wire x1="7.62" y1="67.31" x2="36.83" y2="68.58" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="A15_SYS">
+<contactref element="J3A" pad="5"/>
+<contactref element="IC9" pad="17"/>
+<wire x1="7.62" y1="64.77" x2="36.83" y2="66.04" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="MAP0">
+<contactref element="IC7" pad="12"/>
+<contactref element="IC8" pad="3"/>
+<wire x1="57.15" y1="21.59" x2="93.98" y2="15.24" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="!CS2">
+<contactref element="IC3" pad="22"/>
+<contactref element="IC4" pad="20"/>
+<wire x1="49.53" y1="20.32" x2="81.28" y2="63.5" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="IC3_31">
+<contactref element="IC3" pad="31"/>
+<contactref element="J1" pad="5"/>
+<contactref element="J1" pad="1"/>
+<wire x1="81.915" y1="34.29" x2="81.28" y2="40.64" width="0" layer="19" extent="1-1"/>
+<wire x1="71.755" y1="34.29" x2="81.915" y2="34.29" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="IC3_29">
+<contactref element="IC3" pad="29"/>
+<contactref element="J1" pad="3"/>
+<wire x1="76.835" y1="34.29" x2="81.28" y2="45.72" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="!ROMMAP">
+<contactref element="IC5" pad="17"/>
+<contactref element="IC4" pad="8"/>
+<wire x1="20.32" y1="11.43" x2="41.91" y2="12.7" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="!BOOT">
+<contactref element="S1" pad="2"/>
+<contactref element="IC5" pad="3"/>
+<wire x1="7.62" y1="3.81" x2="62.23" y2="3.81" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="!OE">
+<contactref element="IC1" pad="24"/>
+<contactref element="IC2" pad="24"/>
+<contactref element="IC3" pad="24"/>
+<contactref element="IC4" pad="21"/>
+<wire x1="62.23" y1="58.42" x2="81.28" y2="58.42" width="0" layer="19" extent="1-1"/>
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+<wire x1="49.53" y1="22.86" x2="43.18" y2="58.42" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="!WE">
+<contactref element="IC1" pad="29"/>
+<contactref element="IC2" pad="29"/>
+<contactref element="IC4" pad="22"/>
+<contactref element="J1" pad="4"/>
+<wire x1="62.23" y1="45.72" x2="79.375" y2="34.29" width="0" layer="19" extent="1-1"/>
+<wire x1="43.18" y1="45.72" x2="62.23" y2="45.72" width="0" layer="19" extent="1-1"/>
+<wire x1="49.53" y1="25.4" x2="43.18" y2="45.72" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="!IOSEL">
+<contactref element="IC5" pad="15"/>
+<contactref element="IC4" pad="10"/>
+<wire x1="25.4" y1="11.43" x2="41.91" y2="7.62" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="MAP2">
+<contactref element="IC7" pad="16"/>
+<contactref element="IC8" pad="13"/>
+<wire x1="64.77" y1="19.05" x2="83.82" y2="15.24" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="INTDIS">
+<contactref element="IC5" pad="19"/>
+</signal>
+<signal name="!JUSTBOOTED">
+<contactref element="S1" pad="3"/>
+<contactref element="IC7" pad="2"/>
+<wire x1="64.77" y1="3.81" x2="76.2" y2="7.62" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="MAPWR">
+<contactref element="IC5" pad="1"/>
+<contactref element="IC7" pad="11"/>
+<contactref element="IC4" pad="17"/>
+<wire x1="49.53" y1="12.7" x2="96.52" y2="15.24" width="0" layer="19" extent="1-1"/>
+<wire x1="2.54" y1="3.81" x2="49.53" y2="12.7" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="N$1">
+<contactref element="IC7" pad="5"/>
+<contactref element="Q1" pad="2"/>
+<wire x1="83.185" y1="3.81" x2="83.82" y2="7.62" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="N$2">
+<contactref element="J2" pad="1"/>
+<contactref element="C1" pad="1"/>
+<contactref element="Q1" pad="3"/>
+<wire x1="81.28" y1="2.54" x2="86.36" y2="2.54" width="0" layer="19" extent="1-1"/>
+<wire x1="73.66" y1="2.54" x2="81.28" y2="2.54" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="80/!40">
+<contactref element="IC4" pad="15"/>
+</signal>
+</signals>
+<errors>
+<approved hash="3,16,ba3e20402127bb59"/>
+<approved hash="3,1,ba3e20402127bb59"/>
+</errors>
+</board>
+</drawing>
+</eagle>
diff --git a/v1.2/abc80-1m-sram.sch b/v1.2/abc80-1m-sram.sch
new file mode 100644
index 0000000..88b91f2
--- /dev/null
+++ b/v1.2/abc80-1m-sram.sch
@@ -0,0 +1,8315 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.7.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="yes"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="no"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="no"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="no"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="no"/>
+<layer number="48" name="Document" color="7" fill="1" visible="no" active="no"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="no" active="no"/>
+<layer number="50" name="dxf" color="7" fill="1" visible="no" active="no"/>
+<layer number="51" name="tDocu" color="7" fill="1" visible="no" active="no"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="no"/>
+<layer number="53" name="tGND_GNDA" color="7" fill="9" visible="no" active="no"/>
+<layer number="54" name="bGND_GNDA" color="1" fill="9" visible="no" active="no"/>
+<layer number="56" name="wert" color="7" fill="1" visible="no" active="no"/>
+<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="99" name="SpiceOrder" color="5" fill="1" visible="no" active="yes"/>
+<layer number="100" name="Muster" color="7" fill="1" visible="no" active="no"/>
+<layer number="101" name="Patch_Top" color="12" fill="4" visible="yes" active="yes"/>
+<layer number="102" name="Vscore" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="104" name="Name" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="116" name="Patch_BOT" color="9" fill="4" visible="yes" active="yes"/>
+<layer number="121" name="_tsilk" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="122" name="_bsilk" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="151" name="HeatSink" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="200" name="200bmp" color="1" fill="10" visible="no" active="no"/>
+<layer number="201" name="201bmp" color="2" fill="1" visible="no" active="no"/>
+<layer number="202" name="202bmp" color="3" fill="1" visible="no" active="no"/>
+<layer number="250" name="Descript" color="3" fill="1" visible="no" active="no"/>
+<layer number="251" name="SMDround" color="12" fill="11" visible="no" active="no"/>
+<layer number="254" name="cooling" color="7" fill="1" visible="yes" active="yes"/>
+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="frames">
+<description>&lt;b&gt;Frames for Sheet and Layout&lt;/b&gt;</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="DINA3_L">
+<frame x1="0" y1="0" x2="388.62" y2="264.16" columns="4" rows="4" layer="94" border-left="no" border-top="no" border-right="no" border-bottom="no"/>
+</symbol>
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+<text x="1.27" y="1.27" size="2.54" layer="94">Date:</text>
+<text x="12.7" y="1.27" size="2.54" layer="94">&gt;LAST_DATE_TIME</text>
+<text x="72.39" y="1.27" size="2.54" layer="94">Sheet:</text>
+<text x="86.36" y="1.27" size="2.54" layer="94">&gt;SHEET</text>
+<text x="88.9" y="11.43" size="2.54" layer="94">REV:</text>
+<text x="1.27" y="19.05" size="2.54" layer="94">TITLE:</text>
+<text x="1.27" y="11.43" size="2.54" layer="94">Document Number:</text>
+<text x="17.78" y="19.05" size="2.54" layer="94">&gt;DRAWING_NAME</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="DINA3_L" prefix="FRAME" uservalue="yes">
+<description>&lt;b&gt;FRAME&lt;/b&gt;&lt;p&gt;
+DIN A3, landscape with extra doc field</description>
+<gates>
+<gate name="G$1" symbol="DINA3_L" x="0" y="0"/>
+<gate name="G$2" symbol="DOCFIELD" x="287.02" y="0" addlevel="must"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="zilog">
+<description>&lt;b&gt;Zilog Z80 Microprocessor Devices&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL40">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt;</description>
+<wire x1="25.4" y1="6.731" x2="-25.4" y2="6.731" width="0.1524" layer="21"/>
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+<pad name="1" x="-24.13" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-21.59" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
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+<pad name="31" x="-1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
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+<pad name="40" x="-24.13" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<text x="-25.908" y="-6.604" size="1.778" layer="25" rot="R90">&gt;NAME</text>
+<text x="-17.145" y="-1.016" size="1.778" layer="27">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="Z80CPU">
+<wire x1="-12.7" y1="-35.56" x2="12.7" y2="-35.56" width="0.4064" layer="94"/>
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+<text x="-12.7" y="31.115" size="1.778" layer="95">&gt;NAME</text>
+<text x="-12.7" y="-38.1" size="1.778" layer="96">&gt;VALUE</text>
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+<pin name="D0" x="17.78" y="-15.24" length="middle" rot="R180"/>
+<pin name="D1" x="17.78" y="-17.78" length="middle" rot="R180"/>
+<pin name="D2" x="17.78" y="-20.32" length="middle" rot="R180"/>
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+<pin name="D6" x="17.78" y="-30.48" length="middle" rot="R180"/>
+<pin name="D7" x="17.78" y="-33.02" length="middle" rot="R180"/>
+<pin name="M1" x="-17.78" y="27.94" length="middle" direction="out" function="dot"/>
+<pin name="MREQ" x="-17.78" y="25.4" length="middle" direction="out" function="dot"/>
+<pin name="IORQ" x="-17.78" y="22.86" length="middle" direction="out" function="dot"/>
+<pin name="RD" x="-17.78" y="20.32" length="middle" direction="out" function="dot"/>
+<pin name="WR" x="-17.78" y="17.78" length="middle" direction="out" function="dot"/>
+<pin name="RFSH" x="-17.78" y="12.7" length="middle" direction="out" function="dot"/>
+<pin name="HALT" x="-17.78" y="7.62" length="middle" direction="out" function="dot"/>
+<pin name="WAIT" x="-17.78" y="2.54" length="middle" direction="in" function="dot"/>
+<pin name="INT" x="-17.78" y="-2.54" length="middle" direction="in" function="dot"/>
+<pin name="NMI" x="-17.78" y="-5.08" length="middle" direction="in" function="dot"/>
+<pin name="RESET" x="-17.78" y="-10.16" length="middle" direction="in" function="dot"/>
+<pin name="BUSRQ" x="-17.78" y="-15.24" length="middle" direction="in" function="dot"/>
+<pin name="BUSAK" x="-17.78" y="-17.78" length="middle" direction="out" function="dot"/>
+<pin name="CLK" x="-17.78" y="-22.86" length="middle" direction="in" function="clk"/>
+<pin name="VCC" x="-17.78" y="-33.02" length="middle" direction="pwr"/>
+<pin name="GND" x="-17.78" y="-27.94" length="middle" direction="pwr"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="Z80CPU" prefix="IC" uservalue="yes">
+<description>&lt;b&gt;Z80 FAMILY DEVICE&lt;/b&gt;</description>
+<gates>
+<gate name="1" symbol="Z80CPU" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="DIL40">
+<connects>
+<connect gate="1" pin="A0" pad="30"/>
+<connect gate="1" pin="A1" pad="31"/>
+<connect gate="1" pin="A10" pad="40"/>
+<connect gate="1" pin="A11" pad="1"/>
+<connect gate="1" pin="A12" pad="2"/>
+<connect gate="1" pin="A13" pad="3"/>
+<connect gate="1" pin="A14" pad="4"/>
+<connect gate="1" pin="A15" pad="5"/>
+<connect gate="1" pin="A2" pad="32"/>
+<connect gate="1" pin="A3" pad="33"/>
+<connect gate="1" pin="A4" pad="34"/>
+<connect gate="1" pin="A5" pad="35"/>
+<connect gate="1" pin="A6" pad="36"/>
+<connect gate="1" pin="A7" pad="37"/>
+<connect gate="1" pin="A8" pad="38"/>
+<connect gate="1" pin="A9" pad="39"/>
+<connect gate="1" pin="BUSAK" pad="23"/>
+<connect gate="1" pin="BUSRQ" pad="25"/>
+<connect gate="1" pin="CLK" pad="6"/>
+<connect gate="1" pin="D0" pad="14"/>
+<connect gate="1" pin="D1" pad="15"/>
+<connect gate="1" pin="D2" pad="12"/>
+<connect gate="1" pin="D3" pad="8"/>
+<connect gate="1" pin="D4" pad="7"/>
+<connect gate="1" pin="D5" pad="9"/>
+<connect gate="1" pin="D6" pad="10"/>
+<connect gate="1" pin="D7" pad="13"/>
+<connect gate="1" pin="GND" pad="29"/>
+<connect gate="1" pin="HALT" pad="18"/>
+<connect gate="1" pin="INT" pad="16"/>
+<connect gate="1" pin="IORQ" pad="20"/>
+<connect gate="1" pin="M1" pad="27"/>
+<connect gate="1" pin="MREQ" pad="19"/>
+<connect gate="1" pin="NMI" pad="17"/>
+<connect gate="1" pin="RD" pad="21"/>
+<connect gate="1" pin="RESET" pad="26"/>
+<connect gate="1" pin="RFSH" pad="28"/>
+<connect gate="1" pin="VCC" pad="11"/>
+<connect gate="1" pin="WAIT" pad="24"/>
+<connect gate="1" pin="WR" pad="22"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="con-lstb">
+<description>&lt;b&gt;Pin Headers&lt;/b&gt;&lt;p&gt;
+Naming:&lt;p&gt;
+MA = male&lt;p&gt;
+# contacts - # rows&lt;p&gt;
+W = angled&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="MA20-1">
+<description>&lt;b&gt;PIN HEADER&lt;/b&gt;</description>
+<wire x1="-24.765" y1="1.27" x2="-23.495" y2="1.27" width="0.1524" layer="21"/>
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+<wire x1="-10.16" y1="0.635" x2="-9.525" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-9.525" y1="1.27" x2="-8.255" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-8.255" y1="1.27" x2="-7.62" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-7.62" y1="-0.635" x2="-8.255" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-8.255" y1="-1.27" x2="-9.525" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-9.525" y1="-1.27" x2="-10.16" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-12.065" y1="1.27" x2="-12.7" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="-0.635" x2="-12.065" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-10.795" y1="-1.27" x2="-12.065" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-7.62" y1="0.635" x2="-6.985" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-6.985" y1="1.27" x2="-5.715" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-5.715" y1="1.27" x2="-5.08" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-0.635" x2="-5.715" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-5.715" y1="-1.27" x2="-6.985" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-6.985" y1="-1.27" x2="-7.62" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="1.27" x2="-3.175" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-3.175" y1="1.27" x2="-2.54" y2="0.635" width="0.1524" layer="21"/>
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+<wire x1="-0.635" y1="1.27" x2="0" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="0" y1="-0.635" x2="-0.635" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-0.635" y1="-1.27" x2="-1.905" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="-1.905" y1="-1.27" x2="-2.54" y2="-0.635" width="0.1524" layer="21"/>
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+<wire x1="13.335" y1="1.27" x2="14.605" y2="1.27" width="0.1524" layer="21"/>
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+<wire x1="15.24" y1="0.635" x2="15.875" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="15.875" y1="1.27" x2="17.145" y2="1.27" width="0.1524" layer="21"/>
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+<wire x1="17.145" y1="-1.27" x2="15.875" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="15.875" y1="-1.27" x2="15.24" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="13.335" y1="1.27" x2="12.7" y2="0.635" width="0.1524" layer="21"/>
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+<wire x1="14.605" y1="-1.27" x2="13.335" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="17.78" y1="0.635" x2="18.415" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="18.415" y1="1.27" x2="19.685" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="19.685" y1="1.27" x2="20.32" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="20.32" y1="-0.635" x2="19.685" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="19.685" y1="-1.27" x2="18.415" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="18.415" y1="-1.27" x2="17.78" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="20.955" y1="1.27" x2="22.225" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="22.225" y1="1.27" x2="22.86" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="22.86" y1="-0.635" x2="22.225" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="22.86" y1="0.635" x2="23.495" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="23.495" y1="1.27" x2="24.765" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="24.765" y1="1.27" x2="25.4" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="25.4" y1="0.635" x2="25.4" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="25.4" y1="-0.635" x2="24.765" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="24.765" y1="-1.27" x2="23.495" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="23.495" y1="-1.27" x2="22.86" y2="-0.635" width="0.1524" layer="21"/>
+<wire x1="20.955" y1="1.27" x2="20.32" y2="0.635" width="0.1524" layer="21"/>
+<wire x1="20.32" y1="-0.635" x2="20.955" y2="-1.27" width="0.1524" layer="21"/>
+<wire x1="22.225" y1="-1.27" x2="20.955" y2="-1.27" width="0.1524" layer="21"/>
+<pad name="1" x="-24.13" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="2" x="-21.59" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="3" x="-19.05" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="4" x="-16.51" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="5" x="-13.97" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="6" x="-11.43" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="7" x="-8.89" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="8" x="-6.35" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="9" x="-3.81" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="10" x="-1.27" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="11" x="1.27" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="12" x="3.81" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="13" x="6.35" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="14" x="8.89" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="15" x="11.43" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="16" x="13.97" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="17" x="16.51" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="18" x="19.05" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="19" x="21.59" y="0" drill="1.016" shape="long" rot="R90"/>
+<pad name="20" x="24.13" y="0" drill="1.016" shape="long" rot="R90"/>
+<text x="-25.4" y="1.651" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="-24.384" y="-2.794" size="1.27" layer="21" ratio="10">1</text>
+<text x="23.241" y="-2.921" size="1.27" layer="21" ratio="10">20</text>
+<text x="-1.905" y="-2.921" size="1.27" layer="21" ratio="10">10</text>
+<text x="-17.78" y="1.651" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-24.4602" y1="-0.3302" x2="-23.7998" y2="0.3302" layer="51"/>
+<rectangle x1="0.9398" y1="-0.3302" x2="1.6002" y2="0.3302" layer="51"/>
+<rectangle x1="-21.9202" y1="-0.3302" x2="-21.2598" y2="0.3302" layer="51"/>
+<rectangle x1="-19.3802" y1="-0.3302" x2="-18.7198" y2="0.3302" layer="51"/>
+<rectangle x1="-16.8402" y1="-0.3302" x2="-16.1798" y2="0.3302" layer="51"/>
+<rectangle x1="-14.3002" y1="-0.3302" x2="-13.6398" y2="0.3302" layer="51"/>
+<rectangle x1="3.4798" y1="-0.3302" x2="4.1402" y2="0.3302" layer="51"/>
+<rectangle x1="6.0198" y1="-0.3302" x2="6.6802" y2="0.3302" layer="51"/>
+<rectangle x1="8.5598" y1="-0.3302" x2="9.2202" y2="0.3302" layer="51"/>
+<rectangle x1="11.0998" y1="-0.3302" x2="11.7602" y2="0.3302" layer="51"/>
+<rectangle x1="-11.7602" y1="-0.3302" x2="-11.0998" y2="0.3302" layer="51"/>
+<rectangle x1="-9.2202" y1="-0.3302" x2="-8.5598" y2="0.3302" layer="51"/>
+<rectangle x1="-6.6802" y1="-0.3302" x2="-6.0198" y2="0.3302" layer="51"/>
+<rectangle x1="-4.1402" y1="-0.3302" x2="-3.4798" y2="0.3302" layer="51"/>
+<rectangle x1="-1.6002" y1="-0.3302" x2="-0.9398" y2="0.3302" layer="51"/>
+<rectangle x1="13.6398" y1="-0.3302" x2="14.3002" y2="0.3302" layer="51"/>
+<rectangle x1="16.1798" y1="-0.3302" x2="16.8402" y2="0.3302" layer="51"/>
+<rectangle x1="18.7198" y1="-0.3302" x2="19.3802" y2="0.3302" layer="51"/>
+<rectangle x1="21.2598" y1="-0.3302" x2="21.9202" y2="0.3302" layer="51"/>
+<rectangle x1="23.7998" y1="-0.3302" x2="24.4602" y2="0.3302" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="MA20-1">
+<wire x1="3.81" y1="-25.4" x2="-1.27" y2="-25.4" width="0.4064" layer="94"/>
+<wire x1="1.27" y1="-17.78" x2="2.54" y2="-17.78" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="-20.32" x2="2.54" y2="-20.32" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="-22.86" x2="2.54" y2="-22.86" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="-12.7" x2="2.54" y2="-12.7" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="-15.24" x2="2.54" y2="-15.24" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="-5.08" x2="2.54" y2="-5.08" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="-7.62" x2="2.54" y2="-7.62" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="-10.16" x2="2.54" y2="-10.16" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="0" x2="2.54" y2="0" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="-2.54" x2="2.54" y2="-2.54" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="7.62" x2="2.54" y2="7.62" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="5.08" x2="2.54" y2="5.08" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="2.54" x2="2.54" y2="2.54" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="15.24" x2="2.54" y2="15.24" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="12.7" x2="2.54" y2="12.7" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="10.16" x2="2.54" y2="10.16" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="20.32" x2="2.54" y2="20.32" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="17.78" x2="2.54" y2="17.78" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="25.4" x2="2.54" y2="25.4" width="0.6096" layer="94"/>
+<wire x1="1.27" y1="22.86" x2="2.54" y2="22.86" width="0.6096" layer="94"/>
+<wire x1="-1.27" y1="27.94" x2="-1.27" y2="-25.4" width="0.4064" layer="94"/>
+<wire x1="3.81" y1="-25.4" x2="3.81" y2="27.94" width="0.4064" layer="94"/>
+<wire x1="-1.27" y1="27.94" x2="3.81" y2="27.94" width="0.4064" layer="94"/>
+<text x="-1.27" y="-27.94" size="1.778" layer="96">&gt;VALUE</text>
+<text x="-1.27" y="28.702" size="1.778" layer="95">&gt;NAME</text>
+<pin name="1" x="7.62" y="-22.86" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="2" x="7.62" y="-20.32" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="3" x="7.62" y="-17.78" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="4" x="7.62" y="-15.24" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="5" x="7.62" y="-12.7" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="6" x="7.62" y="-10.16" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="7" x="7.62" y="-7.62" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="8" x="7.62" y="-5.08" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="9" x="7.62" y="-2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="10" x="7.62" y="0" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="11" x="7.62" y="2.54" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="12" x="7.62" y="5.08" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="13" x="7.62" y="7.62" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="14" x="7.62" y="10.16" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="15" x="7.62" y="12.7" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="16" x="7.62" y="15.24" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="17" x="7.62" y="17.78" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="18" x="7.62" y="20.32" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="19" x="7.62" y="22.86" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+<pin name="20" x="7.62" y="25.4" visible="pad" length="middle" direction="pas" swaplevel="1" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="MA20-1" prefix="SV" uservalue="yes">
+<description>&lt;b&gt;PIN HEADER&lt;/b&gt;</description>
+<gates>
+<gate name="1" symbol="MA20-1" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="MA20-1">
+<connects>
+<connect gate="1" pin="1" pad="1"/>
+<connect gate="1" pin="10" pad="10"/>
+<connect gate="1" pin="11" pad="11"/>
+<connect gate="1" pin="12" pad="12"/>
+<connect gate="1" pin="13" pad="13"/>
+<connect gate="1" pin="14" pad="14"/>
+<connect gate="1" pin="15" pad="15"/>
+<connect gate="1" pin="16" pad="16"/>
+<connect gate="1" pin="17" pad="17"/>
+<connect gate="1" pin="18" pad="18"/>
+<connect gate="1" pin="19" pad="19"/>
+<connect gate="1" pin="2" pad="2"/>
+<connect gate="1" pin="20" pad="20"/>
+<connect gate="1" pin="3" pad="3"/>
+<connect gate="1" pin="4" pad="4"/>
+<connect gate="1" pin="5" pad="5"/>
+<connect gate="1" pin="6" pad="6"/>
+<connect gate="1" pin="7" pad="7"/>
+<connect gate="1" pin="8" pad="8"/>
+<connect gate="1" pin="9" pad="9"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="unknown" constant="no"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="supply1">
+<description>&lt;b&gt;Supply Symbols&lt;/b&gt;&lt;p&gt;
+ GND, VCC, 0V, +5V, -5V, etc.&lt;p&gt;
+ Please keep in mind, that these devices are necessary for the
+ automatic wiring of the supply signals.&lt;p&gt;
+ The pin name defined in the symbol is identical to the net which is to be wired automatically.&lt;p&gt;
+ In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.&lt;p&gt;
+ &lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="GND">
+<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
+<text x="-2.54" y="-2.54" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
+</symbol>
+<symbol name="VCC">
+<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/>
+<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">&gt;VALUE</text>
+<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="GND" prefix="GND">
+<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
+<gates>
+<gate name="1" symbol="GND" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="VCC" prefix="P+">
+<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
+<gates>
+<gate name="VCC" symbol="VCC" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="memory-bsi">
+<description>BSI sram memory modules
+
+BS64LV4006 and BS64LV256
+
+luc@tan.nu</description>
+<packages>
+<package name="DIL-32">
+<wire x1="20.32" y1="6.731" x2="-20.32" y2="6.731" width="0.1524" layer="21"/>
+<wire x1="-20.32" y1="-6.731" x2="20.32" y2="-6.731" width="0.1524" layer="21"/>
+<wire x1="20.32" y1="6.731" x2="20.32" y2="-6.731" width="0.1524" layer="21"/>
+<wire x1="-20.32" y1="6.731" x2="-20.32" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-20.32" y1="-6.731" x2="-20.32" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-20.32" y1="1.016" x2="-20.32" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
+<pad name="1" x="-19.05" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="-3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="-1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="-6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="-8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="19.05" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="17" x="19.05" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="18" x="16.51" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="19" x="13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="20" x="11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="21" x="8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="22" x="6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="23" x="3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="24" x="1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="25" x="-1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="26" x="-3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="27" x="-6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="28" x="-8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="29" x="-11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="30" x="-13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="31" x="-16.51" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="32" x="-19.05" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<text x="-20.701" y="-6.604" size="1.778" layer="25" rot="R90">&gt;NAME</text>
+<text x="-16.891" y="-0.889" size="1.778" layer="27">&gt;VALUE</text>
+</package>
+<package name="SOP-32">
+<wire x1="10.22" y1="-4.5" x2="-10.22" y2="-4.5" width="0.2032" layer="51"/>
+<wire x1="-10.22" y1="-4.5" x2="-10.22" y2="-4" width="0.2032" layer="51"/>
+<wire x1="-10.22" y1="-4" x2="-10.22" y2="4.5" width="0.2032" layer="51"/>
+<wire x1="-10.22" y1="4.5" x2="10.22" y2="4.5" width="0.2032" layer="51"/>
+<wire x1="10.22" y1="-4" x2="-10.22" y2="-4" width="0.2032" layer="51"/>
+<wire x1="10.22" y1="4.5" x2="10.22" y2="-4" width="0.2032" layer="51"/>
+<wire x1="10.22" y1="-4" x2="10.22" y2="-4.5" width="0.2032" layer="51"/>
+<smd name="2" x="-8.255" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="13" x="5.715" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="1" x="-9.525" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="3" x="-6.985" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="4" x="-5.715" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="14" x="6.985" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="12" x="4.445" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="11" x="3.175" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="6" x="-3.175" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="9" x="0.635" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="5" x="-4.445" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="7" x="-1.905" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="10" x="1.905" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="8" x="-0.635" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="15" x="8.255" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="16" x="9.525" y="-5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="17" x="9.525" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="18" x="8.255" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="19" x="6.985" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="20" x="5.715" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="21" x="4.445" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="22" x="3.175" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="23" x="1.905" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="24" x="0.635" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="25" x="-0.635" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="26" x="-1.905" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="27" x="-3.175" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="28" x="-4.445" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="29" x="-5.715" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="30" x="-6.985" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="31" x="-8.255" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<smd name="32" x="-9.525" y="5.4" dx="0.6" dy="2.2" layer="1"/>
+<text x="-10.668" y="-4.445" size="1.27" layer="25" rot="R90">&gt;NAME</text>
+<text x="-9.017" y="-0.508" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-9.77" y1="-6.12" x2="-9.28" y2="-4.6" layer="51"/>
+<rectangle x1="-8.5" y1="-6.12" x2="-8.01" y2="-4.6" layer="51"/>
+<rectangle x1="-7.23" y1="-6.12" x2="-6.74" y2="-4.6" layer="51"/>
+<rectangle x1="-5.96" y1="-6.12" x2="-5.47" y2="-4.6" layer="51"/>
+<rectangle x1="-4.69" y1="-6.12" x2="-4.2" y2="-4.6" layer="51"/>
+<rectangle x1="-3.42" y1="-6.12" x2="-2.93" y2="-4.6" layer="51"/>
+<rectangle x1="-2.15" y1="-6.12" x2="-1.66" y2="-4.6" layer="51"/>
+<rectangle x1="-0.88" y1="-6.12" x2="-0.39" y2="-4.6" layer="51"/>
+<rectangle x1="0.39" y1="-6.12" x2="0.88" y2="-4.6" layer="51"/>
+<rectangle x1="1.66" y1="-6.12" x2="2.15" y2="-4.6" layer="51"/>
+<rectangle x1="2.93" y1="-6.12" x2="3.42" y2="-4.6" layer="51"/>
+<rectangle x1="4.2" y1="-6.12" x2="4.69" y2="-4.6" layer="51"/>
+<rectangle x1="5.47" y1="-6.12" x2="5.96" y2="-4.6" layer="51"/>
+<rectangle x1="6.74" y1="-6.12" x2="7.23" y2="-4.6" layer="51"/>
+<rectangle x1="8.01" y1="-6.12" x2="8.5" y2="-4.6" layer="51"/>
+<rectangle x1="9.28" y1="-6.12" x2="9.77" y2="-4.6" layer="51"/>
+<rectangle x1="9.28" y1="4.6" x2="9.77" y2="6.12" layer="51"/>
+<rectangle x1="8.01" y1="4.6" x2="8.5" y2="6.12" layer="51"/>
+<rectangle x1="6.74" y1="4.6" x2="7.23" y2="6.12" layer="51"/>
+<rectangle x1="5.47" y1="4.6" x2="5.96" y2="6.12" layer="51"/>
+<rectangle x1="4.2" y1="4.6" x2="4.69" y2="6.12" layer="51"/>
+<rectangle x1="2.93" y1="4.6" x2="3.42" y2="6.12" layer="51"/>
+<rectangle x1="1.66" y1="4.6" x2="2.15" y2="6.12" layer="51"/>
+<rectangle x1="0.39" y1="4.6" x2="0.88" y2="6.12" layer="51"/>
+<rectangle x1="-0.88" y1="4.6" x2="-0.39" y2="6.12" layer="51"/>
+<rectangle x1="-2.15" y1="4.6" x2="-1.66" y2="6.12" layer="51"/>
+<rectangle x1="-3.42" y1="4.6" x2="-2.93" y2="6.12" layer="51"/>
+<rectangle x1="-4.69" y1="4.6" x2="-4.2" y2="6.12" layer="51"/>
+<rectangle x1="-5.96" y1="4.6" x2="-5.47" y2="6.12" layer="51"/>
+<rectangle x1="-7.23" y1="4.6" x2="-6.74" y2="6.12" layer="51"/>
+<rectangle x1="-8.5" y1="4.6" x2="-8.01" y2="6.12" layer="51"/>
+<rectangle x1="-9.77" y1="4.6" x2="-9.28" y2="6.12" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="BS62LV4006">
+<wire x1="-10.16" y1="-35.56" x2="7.62" y2="-35.56" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="27.94" x2="7.62" y2="-35.56" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="27.94" x2="-10.16" y2="27.94" width="0.4064" layer="94"/>
+<wire x1="-10.16" y1="-35.56" x2="-10.16" y2="27.94" width="0.4064" layer="94"/>
+<text x="-10.16" y="28.575" size="1.778" layer="95">&gt;NAME</text>
+<text x="-10.16" y="-38.1" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="A0" x="-15.24" y="25.4" length="middle" direction="in"/>
+<pin name="A1" x="-15.24" y="22.86" length="middle" direction="in"/>
+<pin name="A2" x="-15.24" y="20.32" length="middle" direction="in"/>
+<pin name="A3" x="-15.24" y="17.78" length="middle" direction="in"/>
+<pin name="A4" x="-15.24" y="15.24" length="middle" direction="in"/>
+<pin name="A5" x="-15.24" y="12.7" length="middle" direction="in"/>
+<pin name="A6" x="-15.24" y="10.16" length="middle" direction="in"/>
+<pin name="A7" x="-15.24" y="7.62" length="middle" direction="in"/>
+<pin name="A8" x="-15.24" y="5.08" length="middle" direction="in"/>
+<pin name="A9" x="-15.24" y="2.54" length="middle" direction="in"/>
+<pin name="A10" x="-15.24" y="0" length="middle" direction="in"/>
+<pin name="A11" x="-15.24" y="-2.54" length="middle" direction="in"/>
+<pin name="A12" x="-15.24" y="-5.08" length="middle" direction="in"/>
+<pin name="A13" x="-15.24" y="-7.62" length="middle" direction="in"/>
+<pin name="A14" x="-15.24" y="-10.16" length="middle" direction="in"/>
+<pin name="!WE" x="-15.24" y="-27.94" length="middle" direction="in"/>
+<pin name="!OE" x="-15.24" y="-30.48" length="middle" direction="in"/>
+<pin name="!CS" x="-15.24" y="-33.02" length="middle" direction="in"/>
+<pin name="I/O0" x="12.7" y="25.4" length="middle" rot="R180"/>
+<pin name="I/O1" x="12.7" y="22.86" length="middle" rot="R180"/>
+<pin name="I/O2" x="12.7" y="20.32" length="middle" rot="R180"/>
+<pin name="I/O3" x="12.7" y="17.78" length="middle" rot="R180"/>
+<pin name="I/O4" x="12.7" y="15.24" length="middle" rot="R180"/>
+<pin name="I/O5" x="12.7" y="12.7" length="middle" rot="R180"/>
+<pin name="I/O6" x="12.7" y="10.16" length="middle" rot="R180"/>
+<pin name="I/O7" x="12.7" y="7.62" length="middle" rot="R180"/>
+<pin name="VSS" x="12.7" y="-33.02" length="middle" direction="pwr" rot="R180"/>
+<pin name="VCC" x="12.7" y="-27.94" length="middle" direction="pwr" rot="R180"/>
+<pin name="A15" x="-15.24" y="-12.7" length="middle" direction="in"/>
+<pin name="A16" x="-15.24" y="-15.24" length="middle" direction="in"/>
+<pin name="A17" x="-15.24" y="-17.78" length="middle" direction="in"/>
+<pin name="A18" x="-15.24" y="-20.32" length="middle" direction="in"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="BS62LV4006">
+<gates>
+<gate name="G$1" symbol="BS62LV4006" x="0" y="2.54"/>
+</gates>
+<devices>
+<device name="P" package="DIL-32">
+<connects>
+<connect gate="G$1" pin="!CS" pad="22"/>
+<connect gate="G$1" pin="!OE" pad="24"/>
+<connect gate="G$1" pin="!WE" pad="29"/>
+<connect gate="G$1" pin="A0" pad="12"/>
+<connect gate="G$1" pin="A1" pad="11"/>
+<connect gate="G$1" pin="A10" pad="23"/>
+<connect gate="G$1" pin="A11" pad="25"/>
+<connect gate="G$1" pin="A12" pad="4"/>
+<connect gate="G$1" pin="A13" pad="28"/>
+<connect gate="G$1" pin="A14" pad="3"/>
+<connect gate="G$1" pin="A15" pad="31"/>
+<connect gate="G$1" pin="A16" pad="2"/>
+<connect gate="G$1" pin="A17" pad="30"/>
+<connect gate="G$1" pin="A18" pad="1"/>
+<connect gate="G$1" pin="A2" pad="10"/>
+<connect gate="G$1" pin="A3" pad="9"/>
+<connect gate="G$1" pin="A4" pad="8"/>
+<connect gate="G$1" pin="A5" pad="7"/>
+<connect gate="G$1" pin="A6" pad="6"/>
+<connect gate="G$1" pin="A7" pad="5"/>
+<connect gate="G$1" pin="A8" pad="27"/>
+<connect gate="G$1" pin="A9" pad="26"/>
+<connect gate="G$1" pin="I/O0" pad="13"/>
+<connect gate="G$1" pin="I/O1" pad="14"/>
+<connect gate="G$1" pin="I/O2" pad="15"/>
+<connect gate="G$1" pin="I/O3" pad="17"/>
+<connect gate="G$1" pin="I/O4" pad="18"/>
+<connect gate="G$1" pin="I/O5" pad="19"/>
+<connect gate="G$1" pin="I/O6" pad="20"/>
+<connect gate="G$1" pin="I/O7" pad="21"/>
+<connect gate="G$1" pin="VCC" pad="32"/>
+<connect gate="G$1" pin="VSS" pad="16"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="S" package="SOP-32">
+<connects>
+<connect gate="G$1" pin="!CS" pad="22"/>
+<connect gate="G$1" pin="!OE" pad="24"/>
+<connect gate="G$1" pin="!WE" pad="29"/>
+<connect gate="G$1" pin="A0" pad="12"/>
+<connect gate="G$1" pin="A1" pad="11"/>
+<connect gate="G$1" pin="A10" pad="23"/>
+<connect gate="G$1" pin="A11" pad="25"/>
+<connect gate="G$1" pin="A12" pad="4"/>
+<connect gate="G$1" pin="A13" pad="28"/>
+<connect gate="G$1" pin="A14" pad="3"/>
+<connect gate="G$1" pin="A15" pad="31"/>
+<connect gate="G$1" pin="A16" pad="2"/>
+<connect gate="G$1" pin="A17" pad="30"/>
+<connect gate="G$1" pin="A18" pad="1"/>
+<connect gate="G$1" pin="A2" pad="10"/>
+<connect gate="G$1" pin="A3" pad="9"/>
+<connect gate="G$1" pin="A4" pad="8"/>
+<connect gate="G$1" pin="A5" pad="7"/>
+<connect gate="G$1" pin="A6" pad="6"/>
+<connect gate="G$1" pin="A7" pad="5"/>
+<connect gate="G$1" pin="A8" pad="27"/>
+<connect gate="G$1" pin="A9" pad="26"/>
+<connect gate="G$1" pin="I/O0" pad="13"/>
+<connect gate="G$1" pin="I/O1" pad="14"/>
+<connect gate="G$1" pin="I/O2" pad="15"/>
+<connect gate="G$1" pin="I/O3" pad="17"/>
+<connect gate="G$1" pin="I/O4" pad="18"/>
+<connect gate="G$1" pin="I/O5" pad="19"/>
+<connect gate="G$1" pin="I/O6" pad="20"/>
+<connect gate="G$1" pin="I/O7" pad="21"/>
+<connect gate="G$1" pin="VCC" pad="32"/>
+<connect gate="G$1" pin="VSS" pad="16"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="74xx-us">
+<description>&lt;b&gt;TTL Devices, 74xx Series with US Symbols&lt;/b&gt;&lt;p&gt;
+Based on the following sources:
+&lt;ul&gt;
+&lt;li&gt;Texas Instruments &lt;i&gt;TTL Data Book&lt;/i&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Volume 1, 1996.
+&lt;li&gt;TTL Data Book, Volume 2 , 1993
+&lt;li&gt;National Seminconductor Databook 1990, ALS/LS Logic
+&lt;li&gt;ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+&lt;li&gt;http://icmaster.com/ViewCompare.asp
+&lt;/ul&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL20">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt;</description>
+<wire x1="12.7" y1="2.921" x2="-12.7" y2="2.921" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="-2.921" x2="12.7" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="12.7" y1="2.921" x2="12.7" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="2.921" x2="-12.7" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="-2.921" x2="-12.7" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-12.7" y1="1.016" x2="-12.7" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
+<pad name="1" x="-11.43" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
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+<wire x1="-4.445" y1="1.5748" x2="-4.445" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="0.508" x2="-4.445" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="-0.508" x2="-4.445" y2="-1.5748" width="0.1524" layer="21"/>
+<wire x1="-4.445" y1="0.508" x2="-4.445" y2="-0.508" width="0.1524" layer="21" curve="-180"/>
+<wire x1="-4.445" y1="-1.6002" x2="4.445" y2="-1.6002" width="0.0508" layer="21"/>
+<smd name="1" x="-3.81" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="14" x="-3.81" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
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+<smd name="12" x="-1.27" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="4" x="0" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="11" x="0" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
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+<smd name="8" x="3.81" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<text x="-3.556" y="-0.508" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<text x="-4.699" y="-1.778" size="1.27" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<rectangle x1="-0.254" y1="1.9558" x2="0.254" y2="3.0988" layer="51"/>
+<rectangle x1="-4.064" y1="-3.0988" x2="-3.556" y2="-1.9558" layer="51"/>
+<rectangle x1="-2.794" y1="-3.0988" x2="-2.286" y2="-1.9558" layer="51"/>
+<rectangle x1="-1.524" y1="-3.0734" x2="-1.016" y2="-1.9304" layer="51"/>
+<rectangle x1="-0.254" y1="-3.0988" x2="0.254" y2="-1.9558" layer="51"/>
+<rectangle x1="-1.524" y1="1.9558" x2="-1.016" y2="3.0988" layer="51"/>
+<rectangle x1="-2.794" y1="1.9558" x2="-2.286" y2="3.0988" layer="51"/>
+<rectangle x1="-4.064" y1="1.9558" x2="-3.556" y2="3.0988" layer="51"/>
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+<rectangle x1="3.556" y1="1.9558" x2="4.064" y2="3.0988" layer="51"/>
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+<rectangle x1="2.286" y1="-3.0988" x2="2.794" y2="-1.9558" layer="51"/>
+<rectangle x1="3.556" y1="-3.0988" x2="4.064" y2="-1.9558" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="74245">
+<wire x1="-7.62" y1="-15.24" x2="7.62" y2="-15.24" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="-15.24" x2="7.62" y2="15.24" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="15.24" x2="-7.62" y2="15.24" width="0.4064" layer="94"/>
+<wire x1="-7.62" y1="15.24" x2="-7.62" y2="-15.24" width="0.4064" layer="94"/>
+<text x="-7.62" y="15.875" size="1.778" layer="95">&gt;NAME</text>
+<text x="-7.62" y="-17.78" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="DIR" x="-12.7" y="-10.16" length="middle" direction="in"/>
+<pin name="A1" x="-12.7" y="12.7" length="middle"/>
+<pin name="A2" x="-12.7" y="10.16" length="middle"/>
+<pin name="A3" x="-12.7" y="7.62" length="middle"/>
+<pin name="A4" x="-12.7" y="5.08" length="middle"/>
+<pin name="A5" x="-12.7" y="2.54" length="middle"/>
+<pin name="A6" x="-12.7" y="0" length="middle"/>
+<pin name="A7" x="-12.7" y="-2.54" length="middle"/>
+<pin name="A8" x="-12.7" y="-5.08" length="middle"/>
+<pin name="B8" x="12.7" y="-5.08" length="middle" rot="R180"/>
+<pin name="B7" x="12.7" y="-2.54" length="middle" rot="R180"/>
+<pin name="B6" x="12.7" y="0" length="middle" rot="R180"/>
+<pin name="B5" x="12.7" y="2.54" length="middle" rot="R180"/>
+<pin name="B4" x="12.7" y="5.08" length="middle" rot="R180"/>
+<pin name="B3" x="12.7" y="7.62" length="middle" rot="R180"/>
+<pin name="B2" x="12.7" y="10.16" length="middle" rot="R180"/>
+<pin name="B1" x="12.7" y="12.7" length="middle" rot="R180"/>
+<pin name="G" x="-12.7" y="-12.7" length="middle" direction="in" function="dot"/>
+</symbol>
+<symbol name="PWRN">
+<text x="-0.635" y="-0.635" size="1.778" layer="95">&gt;NAME</text>
+<text x="1.905" y="-7.62" size="1.27" layer="95" rot="R90">GND</text>
+<text x="1.905" y="5.08" size="1.27" layer="95" rot="R90">VCC</text>
+<pin name="GND" x="0" y="-10.16" visible="pad" direction="pwr" rot="R90"/>
+<pin name="VCC" x="0" y="10.16" visible="pad" direction="pwr" rot="R270"/>
+</symbol>
+<symbol name="7402">
+<wire x1="-1.27" y1="5.08" x2="-7.62" y2="5.08" width="0.4064" layer="94"/>
+<wire x1="-1.27" y1="-5.08" x2="-7.62" y2="-5.08" width="0.4064" layer="94"/>
+<wire x1="-7.62" y1="2.54" x2="-6.096" y2="2.54" width="0.1524" layer="94"/>
+<wire x1="-7.62" y1="-2.54" x2="-6.096" y2="-2.54" width="0.1524" layer="94"/>
+<wire x1="-1.2446" y1="-5.0678" x2="7.5439" y2="0.0507" width="0.4064" layer="94" curve="60.147106" cap="flat"/>
+<wire x1="-1.2446" y1="5.0678" x2="7.5442" y2="-0.0505" width="0.4064" layer="94" curve="-60.148802" cap="flat"/>
+<wire x1="-7.62" y1="5.08" x2="-7.62" y2="-5.08" width="0.4064" layer="94" curve="-90"/>
+<text x="-7.62" y="5.715" size="1.778" layer="95">&gt;NAME</text>
+<text x="-7.62" y="-7.62" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="O" x="12.7" y="0" visible="pad" length="middle" direction="out" function="dot" rot="R180"/>
+<pin name="I0" x="-12.7" y="2.54" visible="pad" length="middle" direction="in" swaplevel="1"/>
+<pin name="I1" x="-12.7" y="-2.54" visible="pad" length="middle" direction="in" swaplevel="1"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="74*245" prefix="IC">
+<description>Octal &lt;b&gt;BUS TRANSCEIVER&lt;/b&gt;, 3-state</description>
+<gates>
+<gate name="A" symbol="74245" x="20.32" y="0"/>
+<gate name="P" symbol="PWRN" x="-5.08" y="0" addlevel="request"/>
+</gates>
+<devices>
+<device name="N" package="DIL20">
+<connects>
+<connect gate="A" pin="A1" pad="2"/>
+<connect gate="A" pin="A2" pad="3"/>
+<connect gate="A" pin="A3" pad="4"/>
+<connect gate="A" pin="A4" pad="5"/>
+<connect gate="A" pin="A5" pad="6"/>
+<connect gate="A" pin="A6" pad="7"/>
+<connect gate="A" pin="A7" pad="8"/>
+<connect gate="A" pin="A8" pad="9"/>
+<connect gate="A" pin="B1" pad="18"/>
+<connect gate="A" pin="B2" pad="17"/>
+<connect gate="A" pin="B3" pad="16"/>
+<connect gate="A" pin="B4" pad="15"/>
+<connect gate="A" pin="B5" pad="14"/>
+<connect gate="A" pin="B6" pad="13"/>
+<connect gate="A" pin="B7" pad="12"/>
+<connect gate="A" pin="B8" pad="11"/>
+<connect gate="A" pin="DIR" pad="1"/>
+<connect gate="A" pin="G" pad="19"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="LS"/>
+</technologies>
+</device>
+<device name="DW" package="SO20W">
+<connects>
+<connect gate="A" pin="A1" pad="2"/>
+<connect gate="A" pin="A2" pad="3"/>
+<connect gate="A" pin="A3" pad="4"/>
+<connect gate="A" pin="A4" pad="5"/>
+<connect gate="A" pin="A5" pad="6"/>
+<connect gate="A" pin="A6" pad="7"/>
+<connect gate="A" pin="A7" pad="8"/>
+<connect gate="A" pin="A8" pad="9"/>
+<connect gate="A" pin="B1" pad="18"/>
+<connect gate="A" pin="B2" pad="17"/>
+<connect gate="A" pin="B3" pad="16"/>
+<connect gate="A" pin="B4" pad="15"/>
+<connect gate="A" pin="B5" pad="14"/>
+<connect gate="A" pin="B6" pad="13"/>
+<connect gate="A" pin="B7" pad="12"/>
+<connect gate="A" pin="B8" pad="11"/>
+<connect gate="A" pin="DIR" pad="1"/>
+<connect gate="A" pin="G" pad="19"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="LS"/>
+</technologies>
+</device>
+<device name="FK" package="LCC20">
+<connects>
+<connect gate="A" pin="A1" pad="2"/>
+<connect gate="A" pin="A2" pad="3"/>
+<connect gate="A" pin="A3" pad="4"/>
+<connect gate="A" pin="A4" pad="5"/>
+<connect gate="A" pin="A5" pad="6"/>
+<connect gate="A" pin="A6" pad="7"/>
+<connect gate="A" pin="A7" pad="8"/>
+<connect gate="A" pin="A8" pad="9"/>
+<connect gate="A" pin="B1" pad="18"/>
+<connect gate="A" pin="B2" pad="17"/>
+<connect gate="A" pin="B3" pad="16"/>
+<connect gate="A" pin="B4" pad="15"/>
+<connect gate="A" pin="B5" pad="14"/>
+<connect gate="A" pin="B6" pad="13"/>
+<connect gate="A" pin="B7" pad="12"/>
+<connect gate="A" pin="B8" pad="11"/>
+<connect gate="A" pin="DIR" pad="1"/>
+<connect gate="A" pin="G" pad="19"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="LS"/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="74*02" prefix="IC">
+<description>Quad 2-input &lt;b&gt;NOR&lt;/b&gt; gate</description>
+<gates>
+<gate name="A" symbol="7402" x="12.7" y="5.08" swaplevel="1"/>
+<gate name="B" symbol="7402" x="12.7" y="-10.16" swaplevel="1"/>
+<gate name="C" symbol="7402" x="43.18" y="5.08" swaplevel="1"/>
+<gate name="D" symbol="7402" x="43.18" y="-10.16" swaplevel="1"/>
+<gate name="P" symbol="PWRN" x="-5.08" y="0" addlevel="request"/>
+</gates>
+<devices>
+<device name="N" package="DIL14">
+<connects>
+<connect gate="A" pin="I0" pad="2"/>
+<connect gate="A" pin="I1" pad="3"/>
+<connect gate="A" pin="O" pad="1"/>
+<connect gate="B" pin="I0" pad="5"/>
+<connect gate="B" pin="I1" pad="6"/>
+<connect gate="B" pin="O" pad="4"/>
+<connect gate="C" pin="I0" pad="8"/>
+<connect gate="C" pin="I1" pad="9"/>
+<connect gate="C" pin="O" pad="10"/>
+<connect gate="D" pin="I0" pad="11"/>
+<connect gate="D" pin="I1" pad="12"/>
+<connect gate="D" pin="O" pad="13"/>
+<connect gate="P" pin="GND" pad="7"/>
+<connect gate="P" pin="VCC" pad="14"/>
+</connects>
+<technologies>
+<technology name=""/>
+<technology name="ALS"/>
+<technology name="AS"/>
+<technology name="LS"/>
+<technology name="S"/>
+</technologies>
+</device>
+<device name="D" package="SO14">
+<connects>
+<connect gate="A" pin="I0" pad="2"/>
+<connect gate="A" pin="I1" pad="3"/>
+<connect gate="A" pin="O" pad="1"/>
+<connect gate="B" pin="I0" pad="5"/>
+<connect gate="B" pin="I1" pad="6"/>
+<connect gate="B" pin="O" pad="4"/>
+<connect gate="C" pin="I0" pad="8"/>
+<connect gate="C" pin="I1" pad="9"/>
+<connect gate="C" pin="O" pad="10"/>
+<connect gate="D" pin="I0" pad="11"/>
+<connect gate="D" pin="I1" pad="12"/>
+<connect gate="D" pin="O" pad="13"/>
+<connect gate="P" pin="GND" pad="7"/>
+<connect gate="P" pin="VCC" pad="14"/>
+</connects>
+<technologies>
+<technology name=""/>
+<technology name="ALS"/>
+<technology name="AS"/>
+<technology name="LS"/>
+<technology name="S"/>
+</technologies>
+</device>
+<device name="FK" package="LCC20">
+<connects>
+<connect gate="A" pin="I0" pad="3"/>
+<connect gate="A" pin="I1" pad="4"/>
+<connect gate="A" pin="O" pad="2"/>
+<connect gate="B" pin="I0" pad="8"/>
+<connect gate="B" pin="I1" pad="9"/>
+<connect gate="B" pin="O" pad="6"/>
+<connect gate="C" pin="I0" pad="12"/>
+<connect gate="C" pin="I1" pad="13"/>
+<connect gate="C" pin="O" pad="14"/>
+<connect gate="D" pin="I0" pad="16"/>
+<connect gate="D" pin="I1" pad="18"/>
+<connect gate="D" pin="O" pad="19"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name=""/>
+<technology name="ALS"/>
+<technology name="AS"/>
+<technology name="LS"/>
+<technology name="S"/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="74xx-eu">
+<description>&lt;b&gt;TTL Devices, 74xx Series with European Symbols&lt;/b&gt;&lt;p&gt;
+Based on the following sources:
+&lt;ul&gt;
+&lt;li&gt;Texas Instruments &lt;i&gt;TTL Data Book&lt;/i&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Volume 1, 1996.
+&lt;li&gt;TTL Data Book, Volume 2 , 1993
+&lt;li&gt;National Seminconductor Databook 1990, ALS/LS Logic
+&lt;li&gt;ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+&lt;li&gt;http://icmaster.com/ViewCompare.asp
+&lt;/ul&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL16">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt;</description>
+<wire x1="10.16" y1="2.921" x2="-10.16" y2="2.921" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="-2.921" x2="10.16" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="10.16" y1="2.921" x2="10.16" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="2.921" x2="-10.16" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="-2.921" x2="-10.16" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="1.016" x2="-10.16" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
+<pad name="1" x="-8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="-1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="-3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="-6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="-8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<text x="-10.541" y="-2.921" size="1.27" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-7.493" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="SO16">
+<description>&lt;b&gt;Small Outline package&lt;/b&gt; 150 mil</description>
+<wire x1="4.699" y1="1.9558" x2="-4.699" y2="1.9558" width="0.1524" layer="51"/>
+<wire x1="4.699" y1="-1.9558" x2="5.08" y2="-1.5748" width="0.1524" layer="21" curve="90"/>
+<wire x1="-5.08" y1="1.5748" x2="-4.699" y2="1.9558" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.699" y1="1.9558" x2="5.08" y2="1.5748" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-5.08" y1="-1.5748" x2="-4.699" y2="-1.9558" width="0.1524" layer="21" curve="90"/>
+<wire x1="-4.699" y1="-1.9558" x2="4.699" y2="-1.9558" width="0.1524" layer="51"/>
+<wire x1="5.08" y1="-1.5748" x2="5.08" y2="1.5748" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="1.5748" x2="-5.08" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0.508" x2="-5.08" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-0.508" x2="-5.08" y2="-1.5748" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0.508" x2="-5.08" y2="-0.508" width="0.1524" layer="21" curve="-180"/>
+<wire x1="-5.08" y1="-1.6002" x2="5.08" y2="-1.6002" width="0.0508" layer="21"/>
+<smd name="1" x="-4.445" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="16" x="-4.445" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="2" x="-3.175" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="3" x="-1.905" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="15" x="-3.175" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="14" x="-1.905" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="4" x="-0.635" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="13" x="-0.635" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="5" x="0.635" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="12" x="0.635" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="6" x="1.905" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="7" x="3.175" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="11" x="1.905" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
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+<rectangle x1="5.461" y1="3.7338" x2="5.969" y2="3.8608" layer="51"/>
+<rectangle x1="4.191" y1="3.8608" x2="4.699" y2="5.334" layer="51"/>
+<rectangle x1="5.461" y1="3.8608" x2="5.969" y2="5.334" layer="51"/>
+<rectangle x1="4.191" y1="-3.8608" x2="4.699" y2="-3.7338" layer="51"/>
+<rectangle x1="5.461" y1="-3.8608" x2="5.969" y2="-3.7338" layer="51"/>
+<rectangle x1="4.191" y1="-5.334" x2="4.699" y2="-3.8608" layer="51"/>
+<rectangle x1="5.461" y1="-5.334" x2="5.969" y2="-3.8608" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="74157">
+<wire x1="-7.62" y1="-15.24" x2="7.62" y2="-15.24" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="-15.24" x2="7.62" y2="15.24" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="15.24" x2="-7.62" y2="15.24" width="0.4064" layer="94"/>
+<wire x1="-7.62" y1="15.24" x2="-7.62" y2="-15.24" width="0.4064" layer="94"/>
+<text x="-7.62" y="15.875" size="1.778" layer="95">&gt;NAME</text>
+<text x="-7.62" y="-17.78" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="!A!/B" x="-12.7" y="-10.16" length="middle" direction="in"/>
+<pin name="1A" x="-12.7" y="12.7" length="middle" direction="in"/>
+<pin name="1B" x="-12.7" y="10.16" length="middle" direction="in"/>
+<pin name="1Y" x="12.7" y="12.7" length="middle" direction="out" rot="R180"/>
+<pin name="2A" x="-12.7" y="7.62" length="middle" direction="in"/>
+<pin name="2B" x="-12.7" y="5.08" length="middle" direction="in"/>
+<pin name="2Y" x="12.7" y="7.62" length="middle" direction="out" rot="R180"/>
+<pin name="3Y" x="12.7" y="2.54" length="middle" direction="out" rot="R180"/>
+<pin name="3B" x="-12.7" y="0" length="middle" direction="in"/>
+<pin name="3A" x="-12.7" y="2.54" length="middle" direction="in"/>
+<pin name="4Y" x="12.7" y="-2.54" length="middle" direction="out" rot="R180"/>
+<pin name="4B" x="-12.7" y="-5.08" length="middle" direction="in"/>
+<pin name="4A" x="-12.7" y="-2.54" length="middle" direction="in"/>
+<pin name="G" x="-12.7" y="-12.7" length="middle" direction="in" function="dot"/>
+</symbol>
+<symbol name="PWRN">
+<text x="-0.635" y="-0.635" size="1.778" layer="95">&gt;NAME</text>
+<text x="1.905" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
+<text x="1.905" y="2.54" size="1.27" layer="95" rot="R90">VCC</text>
+<pin name="GND" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
+<pin name="VCC" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
+</symbol>
+<symbol name="74273">
+<wire x1="-7.62" y1="-15.24" x2="7.62" y2="-15.24" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="-15.24" x2="7.62" y2="15.24" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="15.24" x2="-7.62" y2="15.24" width="0.4064" layer="94"/>
+<wire x1="-7.62" y1="15.24" x2="-7.62" y2="-15.24" width="0.4064" layer="94"/>
+<text x="-7.62" y="15.875" size="1.778" layer="95">&gt;NAME</text>
+<text x="-7.62" y="-17.78" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="CLR" x="-12.7" y="-12.7" length="middle" direction="in" function="dot"/>
+<pin name="Q1" x="12.7" y="12.7" length="middle" direction="out" rot="R180"/>
+<pin name="D1" x="-12.7" y="12.7" length="middle" direction="in"/>
+<pin name="D2" x="-12.7" y="10.16" length="middle" direction="in"/>
+<pin name="Q2" x="12.7" y="10.16" length="middle" direction="out" rot="R180"/>
+<pin name="Q3" x="12.7" y="7.62" length="middle" direction="out" rot="R180"/>
+<pin name="D3" x="-12.7" y="7.62" length="middle" direction="in"/>
+<pin name="D4" x="-12.7" y="5.08" length="middle" direction="in"/>
+<pin name="Q4" x="12.7" y="5.08" length="middle" direction="out" rot="R180"/>
+<pin name="CLK" x="-12.7" y="-10.16" length="middle" direction="in" function="clk"/>
+<pin name="Q5" x="12.7" y="2.54" length="middle" direction="out" rot="R180"/>
+<pin name="D5" x="-12.7" y="2.54" length="middle" direction="in"/>
+<pin name="D6" x="-12.7" y="0" length="middle" direction="in"/>
+<pin name="Q6" x="12.7" y="0" length="middle" direction="out" rot="R180"/>
+<pin name="Q7" x="12.7" y="-2.54" length="middle" direction="out" rot="R180"/>
+<pin name="D7" x="-12.7" y="-2.54" length="middle" direction="in"/>
+<pin name="D8" x="-12.7" y="-5.08" length="middle" direction="in"/>
+<pin name="Q8" x="12.7" y="-5.08" length="middle" direction="out" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="74*157" prefix="IC">
+<description>Quadruple 2-line to 1-line data &lt;b&gt;SELECTOR/MULTIPLEXER&lt;/b&gt;</description>
+<gates>
+<gate name="A" symbol="74157" x="20.32" y="0"/>
+<gate name="P" symbol="PWRN" x="-5.08" y="0" addlevel="request"/>
+</gates>
+<devices>
+<device name="N" package="DIL16">
+<connects>
+<connect gate="A" pin="!A!/B" pad="1"/>
+<connect gate="A" pin="1A" pad="2"/>
+<connect gate="A" pin="1B" pad="3"/>
+<connect gate="A" pin="1Y" pad="4"/>
+<connect gate="A" pin="2A" pad="5"/>
+<connect gate="A" pin="2B" pad="6"/>
+<connect gate="A" pin="2Y" pad="7"/>
+<connect gate="A" pin="3A" pad="11"/>
+<connect gate="A" pin="3B" pad="10"/>
+<connect gate="A" pin="3Y" pad="9"/>
+<connect gate="A" pin="4A" pad="14"/>
+<connect gate="A" pin="4B" pad="13"/>
+<connect gate="A" pin="4Y" pad="12"/>
+<connect gate="A" pin="G" pad="15"/>
+<connect gate="P" pin="GND" pad="8"/>
+<connect gate="P" pin="VCC" pad="16"/>
+</connects>
+<technologies>
+<technology name=""/>
+<technology name="AC"/>
+<technology name="ACT"/>
+<technology name="HC"/>
+<technology name="HCT"/>
+<technology name="LS"/>
+<technology name="S"/>
+</technologies>
+</device>
+<device name="D" package="SO16">
+<connects>
+<connect gate="A" pin="!A!/B" pad="1"/>
+<connect gate="A" pin="1A" pad="2"/>
+<connect gate="A" pin="1B" pad="3"/>
+<connect gate="A" pin="1Y" pad="4"/>
+<connect gate="A" pin="2A" pad="5"/>
+<connect gate="A" pin="2B" pad="6"/>
+<connect gate="A" pin="2Y" pad="7"/>
+<connect gate="A" pin="3A" pad="11"/>
+<connect gate="A" pin="3B" pad="10"/>
+<connect gate="A" pin="3Y" pad="9"/>
+<connect gate="A" pin="4A" pad="14"/>
+<connect gate="A" pin="4B" pad="13"/>
+<connect gate="A" pin="4Y" pad="12"/>
+<connect gate="A" pin="G" pad="15"/>
+<connect gate="P" pin="GND" pad="8"/>
+<connect gate="P" pin="VCC" pad="16"/>
+</connects>
+<technologies>
+<technology name=""/>
+<technology name="AC"/>
+<technology name="ACT"/>
+<technology name="HC"/>
+<technology name="HCT"/>
+<technology name="LS"/>
+<technology name="S"/>
+</technologies>
+</device>
+<device name="FK" package="LCC20">
+<connects>
+<connect gate="A" pin="!A!/B" pad="2"/>
+<connect gate="A" pin="1A" pad="3"/>
+<connect gate="A" pin="1B" pad="4"/>
+<connect gate="A" pin="1Y" pad="5"/>
+<connect gate="A" pin="2A" pad="7"/>
+<connect gate="A" pin="2B" pad="8"/>
+<connect gate="A" pin="2Y" pad="9"/>
+<connect gate="A" pin="3A" pad="14"/>
+<connect gate="A" pin="3B" pad="13"/>
+<connect gate="A" pin="3Y" pad="12"/>
+<connect gate="A" pin="4A" pad="18"/>
+<connect gate="A" pin="4B" pad="17"/>
+<connect gate="A" pin="4Y" pad="15"/>
+<connect gate="A" pin="G" pad="19"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="AC"/>
+<technology name="ACT"/>
+<technology name="HC"/>
+<technology name="HCT"/>
+<technology name="LS"/>
+<technology name="S"/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="74*273" prefix="IC">
+<description>Octal D type &lt;b&gt;FLIP FLOP&lt;/b&gt;, clear</description>
+<gates>
+<gate name="A" symbol="74273" x="20.32" y="0"/>
+<gate name="P" symbol="PWRN" x="-5.08" y="0" addlevel="request"/>
+</gates>
+<devices>
+<device name="N" package="DIL20">
+<connects>
+<connect gate="A" pin="CLK" pad="11"/>
+<connect gate="A" pin="CLR" pad="1"/>
+<connect gate="A" pin="D1" pad="3"/>
+<connect gate="A" pin="D2" pad="4"/>
+<connect gate="A" pin="D3" pad="7"/>
+<connect gate="A" pin="D4" pad="8"/>
+<connect gate="A" pin="D5" pad="13"/>
+<connect gate="A" pin="D6" pad="14"/>
+<connect gate="A" pin="D7" pad="17"/>
+<connect gate="A" pin="D8" pad="18"/>
+<connect gate="A" pin="Q1" pad="2"/>
+<connect gate="A" pin="Q2" pad="5"/>
+<connect gate="A" pin="Q3" pad="6"/>
+<connect gate="A" pin="Q4" pad="9"/>
+<connect gate="A" pin="Q5" pad="12"/>
+<connect gate="A" pin="Q6" pad="15"/>
+<connect gate="A" pin="Q7" pad="16"/>
+<connect gate="A" pin="Q8" pad="19"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name=""/>
+<technology name="AC"/>
+<technology name="ACT"/>
+<technology name="HC"/>
+<technology name="HCT"/>
+</technologies>
+</device>
+<device name="DW" package="SO20W">
+<connects>
+<connect gate="A" pin="CLK" pad="11"/>
+<connect gate="A" pin="CLR" pad="1"/>
+<connect gate="A" pin="D1" pad="3"/>
+<connect gate="A" pin="D2" pad="4"/>
+<connect gate="A" pin="D3" pad="7"/>
+<connect gate="A" pin="D4" pad="8"/>
+<connect gate="A" pin="D5" pad="13"/>
+<connect gate="A" pin="D6" pad="14"/>
+<connect gate="A" pin="D7" pad="17"/>
+<connect gate="A" pin="D8" pad="18"/>
+<connect gate="A" pin="Q1" pad="2"/>
+<connect gate="A" pin="Q2" pad="5"/>
+<connect gate="A" pin="Q3" pad="6"/>
+<connect gate="A" pin="Q4" pad="9"/>
+<connect gate="A" pin="Q5" pad="12"/>
+<connect gate="A" pin="Q6" pad="15"/>
+<connect gate="A" pin="Q7" pad="16"/>
+<connect gate="A" pin="Q8" pad="19"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="AC"/>
+<technology name="ACT"/>
+<technology name="HC"/>
+<technology name="HCT"/>
+<technology name="LS"/>
+</technologies>
+</device>
+<device name="FK" package="LCC20">
+<connects>
+<connect gate="A" pin="CLK" pad="11"/>
+<connect gate="A" pin="CLR" pad="1"/>
+<connect gate="A" pin="D1" pad="3"/>
+<connect gate="A" pin="D2" pad="4"/>
+<connect gate="A" pin="D3" pad="7"/>
+<connect gate="A" pin="D4" pad="8"/>
+<connect gate="A" pin="D5" pad="13"/>
+<connect gate="A" pin="D6" pad="14"/>
+<connect gate="A" pin="D7" pad="17"/>
+<connect gate="A" pin="D8" pad="18"/>
+<connect gate="A" pin="Q1" pad="2"/>
+<connect gate="A" pin="Q2" pad="5"/>
+<connect gate="A" pin="Q3" pad="6"/>
+<connect gate="A" pin="Q4" pad="9"/>
+<connect gate="A" pin="Q5" pad="12"/>
+<connect gate="A" pin="Q6" pad="15"/>
+<connect gate="A" pin="Q7" pad="16"/>
+<connect gate="A" pin="Q8" pad="19"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="AC"/>
+<technology name="ACT"/>
+<technology name="HC"/>
+<technology name="HCT"/>
+<technology name="LS"/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="pal">
+<description>&lt;b&gt;PALs&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL24-3">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt; 0.3 inch</description>
+<wire x1="-14.986" y1="-0.635" x2="-14.986" y2="-2.794" width="0.1524" layer="21"/>
+<wire x1="-14.986" y1="0.635" x2="-14.986" y2="-0.635" width="0.1524" layer="21" curve="-180"/>
+<wire x1="14.986" y1="-2.794" x2="14.986" y2="2.794" width="0.1524" layer="21"/>
+<wire x1="-14.986" y1="-2.794" x2="14.986" y2="-2.794" width="0.1524" layer="21"/>
+<wire x1="-14.986" y1="2.794" x2="14.986" y2="2.794" width="0.1524" layer="21"/>
+<wire x1="-14.986" y1="2.794" x2="-14.986" y2="0.635" width="0.1524" layer="21"/>
+<pad name="1" x="-13.97" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-11.43" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="-3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="-1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="11.43" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="13.97" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="13.97" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="11.43" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="17" x="3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="18" x="1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="19" x="-1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="20" x="-3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="21" x="-6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="22" x="-8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="23" x="-11.43" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="24" x="-13.97" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<text x="-15.2908" y="-2.667" size="1.778" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-13.462" y="-0.889" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="22V10">
+<wire x1="-7.62" y1="15.24" x2="7.62" y2="15.24" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="-20.32" x2="7.62" y2="15.24" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="-20.32" x2="-7.62" y2="-20.32" width="0.4064" layer="94"/>
+<wire x1="-7.62" y1="15.24" x2="-7.62" y2="-20.32" width="0.4064" layer="94"/>
+<text x="-7.62" y="15.875" size="1.778" layer="95">&gt;NAME</text>
+<text x="-7.62" y="-22.86" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="I0" x="-12.7" y="7.62" length="middle" direction="in"/>
+<pin name="I1" x="-12.7" y="5.08" length="middle" direction="in"/>
+<pin name="I2" x="-12.7" y="2.54" length="middle" direction="in"/>
+<pin name="I3" x="-12.7" y="0" length="middle" direction="in"/>
+<pin name="I4" x="-12.7" y="-2.54" length="middle" direction="in"/>
+<pin name="I5" x="-12.7" y="-5.08" length="middle" direction="in"/>
+<pin name="I6" x="-12.7" y="-7.62" length="middle" direction="in"/>
+<pin name="I7" x="-12.7" y="-10.16" length="middle" direction="in"/>
+<pin name="I8" x="-12.7" y="-12.7" length="middle" direction="in"/>
+<pin name="O1" x="12.7" y="-12.7" length="middle" function="dot" rot="R180"/>
+<pin name="O2" x="12.7" y="-10.16" length="middle" function="dot" rot="R180"/>
+<pin name="O3" x="12.7" y="-7.62" length="middle" function="dot" rot="R180"/>
+<pin name="O4" x="12.7" y="-5.08" length="middle" function="dot" rot="R180"/>
+<pin name="O5" x="12.7" y="-2.54" length="middle" function="dot" rot="R180"/>
+<pin name="O6" x="12.7" y="0" length="middle" function="dot" rot="R180"/>
+<pin name="O7" x="12.7" y="2.54" length="middle" function="dot" rot="R180"/>
+<pin name="I9" x="-12.7" y="-15.24" length="middle" direction="in"/>
+<pin name="O0" x="12.7" y="-15.24" length="middle" function="dot" rot="R180"/>
+<pin name="CLK/I0" x="-12.7" y="12.7" length="middle" direction="in" function="clk"/>
+<pin name="I10" x="-12.7" y="-17.78" length="middle" direction="in"/>
+<pin name="O8" x="12.7" y="5.08" length="middle" function="dot" rot="R180"/>
+<pin name="O9" x="12.7" y="7.62" length="middle" function="dot" rot="R180"/>
+</symbol>
+<symbol name="PWRN">
+<text x="-0.635" y="-0.635" size="1.778" layer="95">&gt;NAME</text>
+<text x="1.905" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
+<text x="1.905" y="2.667" size="1.27" layer="95" rot="R90">VCC</text>
+<pin name="GND" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
+<pin name="VCC" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="22V10" prefix="IC" uservalue="yes">
+<description>&lt;b&gt;PAL&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="22V10" x="0" y="0"/>
+<gate name="P" symbol="PWRN" x="-30.48" y="0" addlevel="request"/>
+</gates>
+<devices>
+<device name="" package="DIL24-3">
+<connects>
+<connect gate="G$1" pin="CLK/I0" pad="1"/>
+<connect gate="G$1" pin="I0" pad="2"/>
+<connect gate="G$1" pin="I1" pad="3"/>
+<connect gate="G$1" pin="I10" pad="13"/>
+<connect gate="G$1" pin="I2" pad="4"/>
+<connect gate="G$1" pin="I3" pad="5"/>
+<connect gate="G$1" pin="I4" pad="6"/>
+<connect gate="G$1" pin="I5" pad="7"/>
+<connect gate="G$1" pin="I6" pad="8"/>
+<connect gate="G$1" pin="I7" pad="9"/>
+<connect gate="G$1" pin="I8" pad="10"/>
+<connect gate="G$1" pin="I9" pad="11"/>
+<connect gate="G$1" pin="O0" pad="14"/>
+<connect gate="G$1" pin="O1" pad="15"/>
+<connect gate="G$1" pin="O2" pad="16"/>
+<connect gate="G$1" pin="O3" pad="17"/>
+<connect gate="G$1" pin="O4" pad="18"/>
+<connect gate="G$1" pin="O5" pad="19"/>
+<connect gate="G$1" pin="O6" pad="20"/>
+<connect gate="G$1" pin="O7" pad="21"/>
+<connect gate="G$1" pin="O8" pad="22"/>
+<connect gate="G$1" pin="O9" pad="23"/>
+<connect gate="P" pin="GND" pad="12"/>
+<connect gate="P" pin="VCC" pad="24"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="GAL22V10D-7LPN" constant="no"/>
+<attribute name="OC_FARNELL" value="1571925" constant="no"/>
+<attribute name="OC_NEWARK" value="97M0480" constant="no"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="rcl">
+<description>&lt;b&gt;Resistors, Capacitors, Inductors&lt;/b&gt;&lt;p&gt;
+Based on the previous libraries:
+&lt;ul&gt;
+&lt;li&gt;r.lbr
+&lt;li&gt;cap.lbr
+&lt;li&gt;cap-fe.lbr
+&lt;li&gt;captant.lbr
+&lt;li&gt;polcap.lbr
+&lt;li&gt;ipc-smd.lbr
+&lt;/ul&gt;
+All SMD packages are defined according to the IPC specifications and CECC&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;&lt;p&gt;
+&lt;p&gt;
+for Electrolyt Capacitors see also :&lt;p&gt;
+www.bccomponents.com &lt;p&gt;
+www.panasonic.com&lt;p&gt;
+www.kemet.com&lt;p&gt;
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf &lt;b&gt;(SANYO)&lt;/b&gt;
+&lt;p&gt;
+for trimmer refence see : &lt;u&gt;www.electrospec-inc.com/cross_references/trimpotcrossref.asp&lt;/u&gt;&lt;p&gt;
+
+&lt;table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0&gt;
+&lt;tr valign="top"&gt;
+
+&lt;! &lt;td width="10"&gt;&amp;nbsp;&lt;/td&gt;
+&lt;td width="90%"&gt;
+
+&lt;b&gt;&lt;font color="#0000FF" size="4"&gt;TRIM-POT CROSS REFERENCE&lt;/font&gt;&lt;/b&gt;
+&lt;P&gt;
+&lt;TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2&gt;
+ &lt;TR&gt;
+ &lt;TD COLSPAN=8&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL&gt;&lt;B&gt;RECTANGULAR MULTI-TURN&lt;/B&gt;&lt;/FONT&gt;
+ &lt;/TD&gt;
+ &lt;/TR&gt;
+ &lt;TR&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;BOURNS&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;BI&amp;nbsp;TECH&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;DALE-VISHAY&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;PHILIPS/MEPCO&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;MURATA&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;PANASONIC&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;
+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;SPECTROL&lt;/FONT&gt;
+ &lt;/B&gt;
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+ &lt;TD ALIGN=CENTER&gt;
+ &lt;B&gt;
+ &lt;FONT SIZE=3 FACE=ARIAL color="#FF0000"&gt;MILSPEC&lt;/FONT&gt;
+ &lt;/B&gt;
+ &lt;/TD&gt;&lt;TD&gt;&amp;nbsp;&lt;/TD&gt;
+ &lt;/TR&gt;
+ &lt;TR&gt;
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+ RT/RTR12&lt;BR&gt;
+ RT/RTR12&lt;BR&gt;
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+ RJ/RJR12&lt;BR&gt;&lt;/FONT&gt;
+ &lt;/TD&gt;
+ &lt;/TR&gt;
+ &lt;TR&gt;
+ &lt;TD COLSPAN=8&gt;&amp;nbsp;
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+<packages>
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+<package name="C1812K">
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+<package name="C2225K">
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+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
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+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
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+<package name="C01005">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;</description>
+<rectangle x1="-0.1999" y1="-0.3" x2="0.1999" y2="0.3" layer="35"/>
+<smd name="1" x="-0.1625" y="0" dx="0.2" dy="0.25" layer="1"/>
+<smd name="2" x="0.1625" y="0" dx="0.2" dy="0.25" layer="1"/>
+<text x="-0.4" y="0.3" size="1.27" layer="25">&gt;NAME</text>
+<text x="-0.4" y="-1.6" size="1.27" layer="27">&gt;VALUE</text>
+<rectangle x1="-0.2" y1="-0.1" x2="-0.075" y2="0.1" layer="51"/>
+<rectangle x1="0.075" y1="-0.1" x2="0.2" y2="0.1" layer="51"/>
+<rectangle x1="-0.15" y1="0.05" x2="0.15" y2="0.1" layer="51"/>
+<rectangle x1="-0.15" y1="-0.1" x2="0.15" y2="-0.05" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="C-US">
+<wire x1="-2.54" y1="0" x2="2.54" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="-1.016" x2="0" y2="-2.54" width="0.1524" layer="94"/>
+<wire x1="0" y1="-1" x2="2.4892" y2="-1.8542" width="0.254" layer="94" curve="-37.878202"/>
+<wire x1="-2.4668" y1="-1.8504" x2="0" y2="-1.0161" width="0.254" layer="94" curve="-37.373024"/>
+<text x="1.016" y="0.635" size="1.778" layer="95">&gt;NAME</text>
+<text x="1.016" y="-4.191" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="1" x="0" y="2.54" visible="off" length="short" direction="pas" swaplevel="1" rot="R270"/>
+<pin name="2" x="0" y="-5.08" visible="off" length="short" direction="pas" swaplevel="1" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="C-US" prefix="C" uservalue="yes">
+<description>&lt;B&gt;CAPACITOR&lt;/B&gt;, American symbol</description>
+<gates>
+<gate name="G$1" symbol="C-US" x="0" y="0"/>
+</gates>
+<devices>
+<device name="C0402" package="C0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C0504" package="C0504">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C0603" package="C0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C0805" package="C0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="C1206" package="C1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1210" package="C1210">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1310" package="C1310">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1608" package="C1608">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1812" package="C1812">
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+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C1825" package="C1825">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C2012" package="C2012">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C3216" package="C3216">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C3225" package="C3225">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C4532" package="C4532">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C4564" package="C4564">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="025-024X044" package="C025-024X044">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+<device name="025-025X050" package="C025-025X050">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="025-030X050" package="C025-030X050">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="025-040X050" package="C025-040X050">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="025-050X050" package="C025-050X050">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="025-060X050" package="C025-060X050">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C025_050-024X070" package="C025_050-024X070">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="025_050-025X075" package="C025_050-025X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="025_050-035X075" package="C025_050-035X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="025_050-045X075" package="C025_050-045X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="025_050-055X075" package="C025_050-055X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="050-024X044" package="C050-024X044">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="050-025X075" package="C050-025X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
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+<technologies>
+<technology name=""/>
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+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+<technology name=""/>
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+</device>
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+<connect gate="G$1" pin="1" pad="1"/>
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+<technology name=""/>
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+</device>
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+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
+<technology name=""/>
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+</device>
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+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
+<technology name=""/>
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+</device>
+<device name="050H075X075" package="C050H075X075">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+<technology name=""/>
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+</device>
+<device name="075-032X103" package="C075-032X103">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="075-042X103" package="C075-042X103">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
+<technology name=""/>
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+</device>
+<device name="075-052X106" package="C075-052X106">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+</device>
+<device name="102-043X133" package="C102-043X133">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="102-054X133" package="C102-054X133">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
+<technology name=""/>
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+</device>
+<device name="102-064X133" package="C102-064X133">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
+<technology name=""/>
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+</device>
+<device name="102_152-062X184" package="C102_152-062X184">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
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+<technology name=""/>
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+</device>
+<device name="150-054X183" package="C150-054X183">
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+<connect gate="G$1" pin="1" pad="1"/>
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+<connect gate="G$1" pin="1" pad="1"/>
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+<technology name=""/>
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+<connect gate="G$1" pin="1" pad="1"/>
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+<connect gate="G$1" pin="1" pad="1"/>
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+</device>
+<device name="150-091X182" package="C150-091X182">
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+<connect gate="G$1" pin="1" pad="1"/>
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+<technology name=""/>
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+</device>
+<device name="225-062X268" package="C225-062X268">
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+<connect gate="G$1" pin="1" pad="1"/>
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+<technology name=""/>
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+</device>
+<device name="225-074X268" package="C225-074X268">
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+<connect gate="G$1" pin="1" pad="1"/>
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+</device>
+<device name="225-087X268" package="C225-087X268">
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+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
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+<connect gate="G$1" pin="1" pad="1"/>
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+<technology name=""/>
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+<connect gate="G$1" pin="1" pad="1"/>
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+</device>
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+<connect gate="G$1" pin="1" pad="1"/>
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+</device>
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+<connect gate="G$1" pin="1" pad="1"/>
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+<connect gate="G$1" pin="1" pad="1"/>
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+</device>
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+<connect gate="G$1" pin="1" pad="1"/>
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+</device>
+<device name="325-137X374" package="C325-137X374">
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+<connect gate="G$1" pin="1" pad="1"/>
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+</device>
+<device name="325-162X374" package="C325-162X374">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+</device>
+<device name="325-182X374" package="C325-182X374">
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+<connect gate="G$1" pin="1" pad="1"/>
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+<technology name=""/>
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+</device>
+<device name="375-192X418" package="C375-192X418">
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+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
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+</device>
+<device name="375-203X418" package="C375-203X418">
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+<technologies>
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+</device>
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+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
+<technology name=""/>
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+</device>
+<device name="375-155X418" package="C375-155X418">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
+<technology name=""/>
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+</device>
+<device name="075-063X106" package="C075-063X106">
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+<connect gate="G$1" pin="1" pad="1"/>
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+</device>
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+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
+<technology name=""/>
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+</device>
+<device name="275-173X316" package="C275-173X316">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
+<technology name=""/>
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+</device>
+<device name="C0402K" package="C0402K">
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+<connect gate="G$1" pin="1" pad="1"/>
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+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="C0603K" package="C0603K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="C0805K" package="C0805K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
+<technology name=""/>
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+</device>
+<device name="C1206K" package="C1206K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
+<technology name=""/>
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+</device>
+<device name="C1210K" package="C1210K">
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+<connect gate="G$1" pin="1" pad="1"/>
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+</connects>
+<technologies>
+<technology name=""/>
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+</device>
+<device name="C1812K" package="C1812K">
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+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
+<technology name=""/>
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+</device>
+<device name="C1825K" package="C1825K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
+<technology name=""/>
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+</device>
+<device name="C2220K" package="C2220K">
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+<connect gate="G$1" pin="1" pad="1"/>
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+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C2225K" package="C2225K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="C0201" package="C0201">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
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+</device>
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+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
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+<technologies>
+<technology name=""/>
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+</device>
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+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="01005" package="C01005">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
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+<technology name=""/>
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+<description>&lt;b&gt;Switches&lt;/b&gt;&lt;p&gt;
+Marquardt, Siemens, C&amp;K, ITT, and others&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
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+<description>&lt;b&gt;TINY SWITCH&lt;/b&gt;&lt;p&gt;
+Source: http://www2.produktinfo.conrad.com/datenblaetter/700000-724999/705152-da-01-de-Subminiaturschalter_TL_36YO.pdf</description>
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+<description>&lt;b&gt;TINY SWITCH&lt;/b&gt; ON - ON&lt;p&gt;
+Source: http://www2.produktinfo.conrad.com/datenblaetter/700000-724999/705152-da-01-de-Subminiaturschalter_TL_36YO.pdf</description>
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+&lt;ul&gt;
+&lt;li&gt;www.atmel.com
+&lt;li&gt;CD-ROM : Configurable Logic Microcontroller Nonvolatile Memory
+&lt;li&gt;CadSoft download site, www.cadsoft.de or www.cadsoftusa.com , file at90smcu_v400.zip
+&lt;li&gt;avr.lbr
+&lt;/ul&gt;
+&lt;author&gt;Revised by librarian@cadsoft.de&lt;/author&gt;</description>
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+<text x="-7.62" y="-20.32" size="1.778" layer="96">&gt;VALUE</text>
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+</symbols>
+<devicesets>
+<deviceset name="ATF16V8B" prefix="IC">
+<description>&lt;b&gt;High perfomance CMOS (electrically erasable) programmable logic device (PLD)&lt;/b&gt;&lt;p&gt;
+ABLE-Atmel-ABEL - P18V8R, P16V8C, P16V8AS, P17V8&lt;br&gt;
+COPL Atmel-WinCUPL - G16V8MS, G16V8MA, G16V8AS, G16V8&lt;br&gt;
+LOG/IC - GAL16V8_R, GAL16V8_G7, GAL16V8_C), GAL16V8&lt;br&gt;
+Tango-PLD - G16V8R, G16V8C, G16V8AS, G16V8&lt;br&gt;
+
+
+Source: http://www.atmel.com/dyn/resources/prod_documents/DOC0364.PDF</description>
+<gates>
+<gate name="G$1" symbol="ATF16V8B" x="0" y="0"/>
+</gates>
+<devices>
+<device name="X" package="TSSOP20">
+<connects>
+<connect gate="G$1" pin="CLK" pad="1"/>
+<connect gate="G$1" pin="GND" pad="10"/>
+<connect gate="G$1" pin="I1" pad="2"/>
+<connect gate="G$1" pin="I2" pad="3"/>
+<connect gate="G$1" pin="I3" pad="4"/>
+<connect gate="G$1" pin="I4" pad="5"/>
+<connect gate="G$1" pin="I5" pad="6"/>
+<connect gate="G$1" pin="I6" pad="7"/>
+<connect gate="G$1" pin="I7" pad="8"/>
+<connect gate="G$1" pin="I8" pad="9"/>
+<connect gate="G$1" pin="O1" pad="19"/>
+<connect gate="G$1" pin="O2" pad="18"/>
+<connect gate="G$1" pin="O3" pad="17"/>
+<connect gate="G$1" pin="O4" pad="16"/>
+<connect gate="G$1" pin="O5" pad="15"/>
+<connect gate="G$1" pin="O6" pad="14"/>
+<connect gate="G$1" pin="O7" pad="13"/>
+<connect gate="G$1" pin="O8" pad="12"/>
+<connect gate="G$1" pin="OE" pad="11"/>
+<connect gate="G$1" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="unknown" constant="no"/>
+</technology>
+</technologies>
+</device>
+<device name="J" package="PLCC20">
+<connects>
+<connect gate="G$1" pin="CLK" pad="1"/>
+<connect gate="G$1" pin="GND" pad="10"/>
+<connect gate="G$1" pin="I1" pad="2"/>
+<connect gate="G$1" pin="I2" pad="3"/>
+<connect gate="G$1" pin="I3" pad="4"/>
+<connect gate="G$1" pin="I4" pad="5"/>
+<connect gate="G$1" pin="I5" pad="6"/>
+<connect gate="G$1" pin="I6" pad="7"/>
+<connect gate="G$1" pin="I7" pad="8"/>
+<connect gate="G$1" pin="I8" pad="9"/>
+<connect gate="G$1" pin="O1" pad="19"/>
+<connect gate="G$1" pin="O2" pad="18"/>
+<connect gate="G$1" pin="O3" pad="17"/>
+<connect gate="G$1" pin="O4" pad="16"/>
+<connect gate="G$1" pin="O5" pad="15"/>
+<connect gate="G$1" pin="O6" pad="14"/>
+<connect gate="G$1" pin="O7" pad="13"/>
+<connect gate="G$1" pin="O8" pad="12"/>
+<connect gate="G$1" pin="OE" pad="11"/>
+<connect gate="G$1" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="ATF16V8CZ-15JU" constant="no"/>
+<attribute name="OC_FARNELL" value="1551767" constant="no"/>
+<attribute name="OC_NEWARK" value="94M6253" constant="no"/>
+</technology>
+</technologies>
+</device>
+<device name="P3" package="DIL20">
+<connects>
+<connect gate="G$1" pin="CLK" pad="1"/>
+<connect gate="G$1" pin="GND" pad="10"/>
+<connect gate="G$1" pin="I1" pad="2"/>
+<connect gate="G$1" pin="I2" pad="3"/>
+<connect gate="G$1" pin="I3" pad="4"/>
+<connect gate="G$1" pin="I4" pad="5"/>
+<connect gate="G$1" pin="I5" pad="6"/>
+<connect gate="G$1" pin="I6" pad="7"/>
+<connect gate="G$1" pin="I7" pad="8"/>
+<connect gate="G$1" pin="I8" pad="9"/>
+<connect gate="G$1" pin="O1" pad="19"/>
+<connect gate="G$1" pin="O2" pad="18"/>
+<connect gate="G$1" pin="O3" pad="17"/>
+<connect gate="G$1" pin="O4" pad="16"/>
+<connect gate="G$1" pin="O5" pad="15"/>
+<connect gate="G$1" pin="O6" pad="14"/>
+<connect gate="G$1" pin="O7" pad="13"/>
+<connect gate="G$1" pin="O8" pad="12"/>
+<connect gate="G$1" pin="OE" pad="11"/>
+<connect gate="G$1" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="ATF16V8CZ-15PU" constant="no"/>
+<attribute name="OC_FARNELL" value="1551768" constant="no"/>
+<attribute name="OC_NEWARK" value="94M6254" constant="no"/>
+</technology>
+</technologies>
+</device>
+<device name="S" package="SO20L">
+<connects>
+<connect gate="G$1" pin="CLK" pad="1"/>
+<connect gate="G$1" pin="GND" pad="10"/>
+<connect gate="G$1" pin="I1" pad="2"/>
+<connect gate="G$1" pin="I2" pad="3"/>
+<connect gate="G$1" pin="I3" pad="4"/>
+<connect gate="G$1" pin="I4" pad="5"/>
+<connect gate="G$1" pin="I5" pad="6"/>
+<connect gate="G$1" pin="I6" pad="7"/>
+<connect gate="G$1" pin="I7" pad="8"/>
+<connect gate="G$1" pin="I8" pad="9"/>
+<connect gate="G$1" pin="O1" pad="19"/>
+<connect gate="G$1" pin="O2" pad="18"/>
+<connect gate="G$1" pin="O3" pad="17"/>
+<connect gate="G$1" pin="O4" pad="16"/>
+<connect gate="G$1" pin="O5" pad="15"/>
+<connect gate="G$1" pin="O6" pad="14"/>
+<connect gate="G$1" pin="O7" pad="13"/>
+<connect gate="G$1" pin="O8" pad="12"/>
+<connect gate="G$1" pin="OE" pad="11"/>
+<connect gate="G$1" pin="VCC" pad="20"/>
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+<attribute name="MPN" value="" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="unknown" constant="no"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="pinhead">
+<description>&lt;b&gt;Pin Header Connectors&lt;/b&gt;&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
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+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="PINHD-1X6" prefix="JP" uservalue="yes">
+<description>&lt;b&gt;PIN HEADER&lt;/b&gt;</description>
+<gates>
+<gate name="A" symbol="PINHD6" x="0" y="-2.54"/>
+</gates>
+<devices>
+<device name="" package="1X06">
+<connects>
+<connect gate="A" pin="1" pad="1"/>
+<connect gate="A" pin="2" pad="2"/>
+<connect gate="A" pin="3" pad="3"/>
+<connect gate="A" pin="4" pad="4"/>
+<connect gate="A" pin="5" pad="5"/>
+<connect gate="A" pin="6" pad="6"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="/90" package="1X06/90">
+<connects>
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+<connect gate="A" pin="2" pad="2"/>
+<connect gate="A" pin="3" pad="3"/>
+<connect gate="A" pin="4" pad="4"/>
+<connect gate="A" pin="5" pad="5"/>
+<connect gate="A" pin="6" pad="6"/>
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+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="PINHD-1X1" prefix="JP" uservalue="yes">
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+<device name="" package="1X01">
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+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
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+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
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+<pad name="2" x="0" y="1.905" drill="0.8128" shape="octagon"/>
+<pad name="1" x="-1.27" y="0" drill="0.8128" shape="octagon"/>
+<text x="3.175" y="0.635" size="1.27" layer="25" ratio="10">&gt;NAME</text>
+<text x="3.175" y="-1.27" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<text x="-0.635" y="0.635" size="1.27" layer="27" ratio="10">2</text>
+<text x="-2.159" y="0" size="1.27" layer="27" ratio="10">1</text>
+<text x="1.143" y="0" size="1.27" layer="27" ratio="10">3</text>
+</package>
+</packages>
+<symbols>
+<symbol name="MOSFET-N-ENH-BDIODE">
+<wire x1="-5.08" y1="-2.54" x2="-3.81" y2="-2.54" width="0.1524" layer="94"/>
+<wire x1="-3.81" y1="-2.54" x2="-3.81" y2="2.54" width="0.1524" layer="94"/>
+<wire x1="-3.048" y1="1.016" x2="-3.048" y2="0" width="0.1524" layer="94"/>
+<wire x1="-3.048" y1="0" x2="-3.048" y2="-1.016" width="0.1524" layer="94"/>
+<wire x1="-3.048" y1="1.778" x2="-3.048" y2="2.794" width="0.1524" layer="94"/>
+<wire x1="-3.048" y1="2.794" x2="-3.048" y2="3.81" width="0.1524" layer="94"/>
+<wire x1="-3.048" y1="-1.778" x2="-3.048" y2="-2.794" width="0.1524" layer="94"/>
+<wire x1="-3.048" y1="-2.794" x2="-3.048" y2="-3.81" width="0.1524" layer="94"/>
+<wire x1="-3.048" y1="0" x2="-2.032" y2="1.016" width="0.1524" layer="94"/>
+<wire x1="-2.032" y1="1.016" x2="-2.032" y2="0" width="0.1524" layer="94"/>
+<wire x1="-2.032" y1="0" x2="-2.032" y2="-1.016" width="0.1524" layer="94"/>
+<wire x1="-2.032" y1="-1.016" x2="-2.54" y2="-0.508" width="0.1524" layer="94"/>
+<wire x1="-2.54" y1="-0.508" x2="-3.048" y2="0" width="0.1524" layer="94"/>
+<wire x1="-2.794" y1="0" x2="-2.54" y2="0.254" width="0.508" layer="94"/>
+<wire x1="-2.54" y1="-0.508" x2="-2.54" y2="-0.254" width="0.1524" layer="94"/>
+<wire x1="-2.54" y1="-0.254" x2="-2.794" y2="0" width="0.508" layer="94"/>
+<wire x1="-2.413" y1="0.381" x2="-2.413" y2="-0.381" width="0.381" layer="94"/>
+<wire x1="-3.048" y1="-2.794" x2="0" y2="-2.794" width="0.1524" layer="94"/>
+<wire x1="0" y1="-2.794" x2="0" y2="-3.556" width="0.1524" layer="94"/>
+<wire x1="0" y1="-3.556" x2="0" y2="-5.588" width="0.1524" layer="94"/>
+<wire x1="-3.048" y1="2.794" x2="0" y2="2.794" width="0.1524" layer="94"/>
+<wire x1="0" y1="2.794" x2="0" y2="3.81" width="0.1524" layer="94"/>
+<wire x1="0" y1="3.81" x2="0" y2="5.588" width="0.1524" layer="94"/>
+<wire x1="-2.032" y1="0" x2="0" y2="0" width="0.1524" layer="94"/>
+<wire x1="0" y1="0" x2="0" y2="-2.794" width="0.1524" layer="94"/>
+<wire x1="0" y1="3.81" x2="2.54" y2="3.81" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="3.81" x2="2.54" y2="0.762" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="-3.556" x2="0" y2="-3.556" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="0.762" x2="1.778" y2="0.762" width="0.1524" layer="94"/>
+<wire x1="1.778" y1="0.762" x2="1.524" y2="0.508" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="0.762" x2="3.302" y2="0.762" width="0.1524" layer="94"/>
+<wire x1="3.302" y1="0.762" x2="3.556" y2="1.016" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="-0.127" x2="2.54" y2="-3.556" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="0.762" x2="1.778" y2="-0.254" width="0.1524" layer="94"/>
+<wire x1="1.778" y1="-0.254" x2="3.302" y2="-0.254" width="0.1524" layer="94"/>
+<wire x1="3.302" y1="-0.254" x2="2.54" y2="0.762" width="0.1524" layer="94"/>
+<wire x1="2.54" y1="0.762" x2="2.54" y2="0.508" width="0.2032" layer="94"/>
+<wire x1="2.54" y1="0.127" x2="2.54" y2="-0.127" width="0.2032" layer="94"/>
+<wire x1="2.54" y1="-0.127" x2="2.032" y2="-0.127" width="0.3048" layer="94"/>
+<wire x1="2.54" y1="-0.127" x2="3.048" y2="-0.127" width="0.3048" layer="94"/>
+<wire x1="2.159" y1="0.127" x2="2.54" y2="0.127" width="0.3048" layer="94"/>
+<wire x1="2.54" y1="0.127" x2="2.921" y2="0.127" width="0.3048" layer="94"/>
+<wire x1="2.921" y1="0.127" x2="2.54" y2="0.508" width="0.3048" layer="94"/>
+<wire x1="2.54" y1="0.508" x2="2.54" y2="0.127" width="0.3048" layer="94"/>
+<wire x1="-2.286" y1="0.508" x2="-2.286" y2="-0.508" width="0.3048" layer="94"/>
+<wire x1="-2.159" y1="-0.762" x2="-2.159" y2="0.762" width="0.3048" layer="94"/>
+<wire x1="2.286" y1="0.254" x2="2.413" y2="0.381" width="0.3048" layer="94"/>
+<circle x="0" y="0" radius="5.6796" width="0.254" layer="94"/>
+<circle x="0" y="3.81" radius="0.127" width="0.508" layer="94"/>
+<circle x="0" y="-3.556" radius="0.127" width="0.508" layer="94"/>
+<text x="-0.508" y="6.35" size="1.27" layer="94" ratio="10" rot="MR0">D</text>
+<text x="-6.096" y="-1.778" size="1.27" layer="94" ratio="10" rot="MR0">G</text>
+<text x="-0.508" y="-7.62" size="1.27" layer="94" ratio="10" rot="MR0">S</text>
+<text x="6.604" y="0.762" size="1.778" layer="95">&gt;NAME</text>
+<text x="6.604" y="-1.524" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="G" x="-10.16" y="-2.54" visible="off" length="middle" direction="hiz"/>
+<pin name="S" x="0" y="-10.16" visible="off" length="middle" rot="R90"/>
+<pin name="D" x="0" y="10.16" visible="off" length="middle" rot="R270"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="2N700*" prefix="Q" uservalue="yes">
+<description>&lt;h3&gt;2N7000, 2N7002, NDS7002A&lt;/h3&gt;
+
+&lt;p&gt;N-channel enhancement mode MOSFET&lt;/p&gt;</description>
+<gates>
+<gate name="G$1" symbol="MOSFET-N-ENH-BDIODE" x="0" y="0"/>
+</gates>
+<devices>
+<device name="_SOT23" package="SOT-23">
+<connects>
+<connect gate="G$1" pin="D" pad="3"/>
+<connect gate="G$1" pin="G" pad="1"/>
+<connect gate="G$1" pin="S" pad="2"/>
+</connects>
+<technologies>
+<technology name="0"/>
+<technology name="2"/>
+<technology name="2A"/>
+</technologies>
+</device>
+<device name="_TO92" package="TO-92">
+<connects>
+<connect gate="G$1" pin="D" pad="3"/>
+<connect gate="G$1" pin="G" pad="2"/>
+<connect gate="G$1" pin="S" pad="1"/>
+</connects>
+<technologies>
+<technology name="0"/>
+<technology name="2"/>
+<technology name="2A"/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0.2032" drill="0">
+</class>
+<class number="1" name="supply" width="0.8128" drill="0">
+</class>
+</classes>
+<parts>
+<part name="FRAME1" library="frames" deviceset="DINA3_L" device="" value="FOO"/>
+<part name="CPU" library="zilog" deviceset="Z80CPU" device="" value="Z80CPU"/>
+<part name="J3A" library="con-lstb" deviceset="MA20-1" device=""/>
+<part name="J3B" library="con-lstb" deviceset="MA20-1" device=""/>
+<part name="GND1" library="supply1" deviceset="GND" device=""/>
+<part name="GND2" library="supply1" deviceset="GND" device=""/>
+<part name="IC1" library="memory-bsi" deviceset="BS62LV4006" device="P" value="512Kx8 SRAM"/>
+<part name="GND4" library="supply1" deviceset="GND" device=""/>
+<part name="IC10" library="74xx-us" deviceset="74*245" device="N" technology="LS" value="74HCT245N"/>
+<part name="IC8" library="74xx-eu" deviceset="74*157" device="N" technology="HCT"/>
+<part name="P+1" library="supply1" deviceset="VCC" device=""/>
+<part name="P+9" library="supply1" deviceset="VCC" device=""/>
+<part name="P+10" library="supply1" deviceset="VCC" device=""/>
+<part name="IC3" library="memory-bsi" deviceset="BS62LV4006" device="P" value="512Kx8 SRAM/flash"/>
+<part name="GND5" library="supply1" deviceset="GND" device=""/>
+<part name="P+2" library="supply1" deviceset="VCC" device=""/>
+<part name="IC4" library="pal" deviceset="22V10" device="" value="22V10-IC4"/>
+<part name="IC6" library="74xx-eu" deviceset="74*273" device="N" technology="HC" value="74HCT273N"/>
+<part name="IC7" library="74xx-eu" deviceset="74*273" device="N" technology="HC" value="74HCT273N"/>
+<part name="P+5" library="supply1" deviceset="VCC" device=""/>
+<part name="GND11" library="supply1" deviceset="GND" device=""/>
+<part name="CC3" library="rcl" deviceset="C-US" device="025-025X050" value="0.1uF"/>
+<part name="CC9" library="rcl" deviceset="C-US" device="025-025X050" value="0.1uF"/>
+<part name="CC8" library="rcl" deviceset="C-US" device="025-025X050" value="0.1uF"/>
+<part name="CC5" library="rcl" deviceset="C-US" device="025-025X050" value="0.1uF"/>
+<part name="P+7" library="supply1" deviceset="VCC" device=""/>
+<part name="P+12" library="supply1" deviceset="VCC" device=""/>
+<part name="P+13" library="supply1" deviceset="VCC" device=""/>
+<part name="P+14" library="supply1" deviceset="VCC" device=""/>
+<part name="GND12" library="supply1" deviceset="GND" device=""/>
+<part name="GND14" library="supply1" deviceset="GND" device=""/>
+<part name="GND17" library="supply1" deviceset="GND" device=""/>
+<part name="GND18" library="supply1" deviceset="GND" device=""/>
+<part name="CC6" library="rcl" deviceset="C-US" device="025-025X050" value="0.1uF"/>
+<part name="CC10" library="rcl" deviceset="C-US" device="025-025X050" value="0.1uF"/>
+<part name="IC2" library="memory-bsi" deviceset="BS62LV4006" device="P" value="512Kx8 SRAM"/>
+<part name="GND7" library="supply1" deviceset="GND" device=""/>
+<part name="P+6" library="supply1" deviceset="VCC" device=""/>
+<part name="CC2" library="rcl" deviceset="C-US" device="025-025X050" value="0.1uF"/>
+<part name="IC5" library="pal" deviceset="22V10" device="" value="22V10-IC5"/>
+<part name="P+11" library="supply1" deviceset="VCC" device=""/>
+<part name="GND16" library="supply1" deviceset="GND" device=""/>
+<part name="CC7" library="rcl" deviceset="C-US" device="025-025X050" value="0.1uF"/>
+<part name="S1" library="switch" deviceset="TL36PO" device="" value="PCB"/>
+<part name="P+17" library="supply1" deviceset="VCC" device=""/>
+<part name="GND3" library="supply1" deviceset="GND" device=""/>
+<part name="GND8" library="supply1" deviceset="GND" device=""/>
+<part name="GND13" library="supply1" deviceset="GND" device=""/>
+<part name="J1" library="pinhead" deviceset="PINHD-1X6" device=""/>
+<part name="IC9" library="atmel" deviceset="ATF16V8B" device="P3" value="16V8-IC9"/>
+<part name="P+3" library="supply1" deviceset="VCC" device=""/>
+<part name="GND6" library="supply1" deviceset="GND" device=""/>
+<part name="P+15" library="supply1" deviceset="VCC" device=""/>
+<part name="P+4" library="supply1" deviceset="VCC" device=""/>
+<part name="GND9" library="supply1" deviceset="GND" device=""/>
+<part name="J2" library="pinhead" deviceset="PINHD-1X1" device="/90"/>
+<part name="C1" library="rcl" deviceset="C-US" device="025-025X050" value="0.1uF"/>
+<part name="GND10" library="supply1" deviceset="GND" device=""/>
+<part name="IC11" library="74xx-us" deviceset="74*02" device="N" technology="LS" value="74HCT02N"/>
+<part name="Q1" library="transistors" deviceset="2N700*" device="_TO92" technology="0"/>
+<part name="CC1" library="rcl" deviceset="C-US" device="025-025X050" value="0.1uF"/>
+<part name="P+16" library="supply1" deviceset="VCC" device=""/>
+<part name="GND15" library="supply1" deviceset="GND" device=""/>
+<part name="CC11" library="rcl" deviceset="C-US" device="025-025X050" value="0.1uF"/>
+<part name="GND19" library="supply1" deviceset="GND" device=""/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+<text x="223.52" y="88.9" size="1.27" layer="97">Address pin
+assignment
+corresponds
+to flash pinout
+(SRAM is
+arbitrary)</text>
+<text x="284.48" y="88.9" size="1.27" layer="97">Address pin
+assignment
+corresponds
+to flash pinout
+(SRAM is
+arbitrary)</text>
+<text x="302.26" y="25.4" size="2.54" layer="94">ABC80 1.5 MB SRAM/flash
+(C) 2020 H. Peter Anvin</text>
+<text x="378.46" y="7.62" size="2.54" layer="94">1.1a</text>
+<text x="243.84" y="17.78" size="1.27" layer="97">1-2, 3-4 for SRAM
+2-3, 4-5 for flash (write enabled)
+2-3, 5-6 for flash (write protected)</text>
+<text x="340.36" y="243.84" size="1.27" layer="97">(Optional) connect to !RESIN!
+F7 pin 12 or bus pin A3</text>
+</plain>
+<instances>
+<instance part="FRAME1" gate="G$1" x="0" y="0"/>
+<instance part="FRAME1" gate="G$2" x="287.02" y="0"/>
+<instance part="CPU" gate="1" x="40.64" y="205.74"/>
+<instance part="J3A" gate="1" x="68.58" y="66.04" rot="R180"/>
+<instance part="J3B" gate="1" x="81.28" y="63.5"/>
+<instance part="GND1" gate="1" x="20.32" y="167.64"/>
+<instance part="GND2" gate="1" x="106.68" y="53.34"/>
+<instance part="IC1" gate="G$1" x="210.82" y="96.52"/>
+<instance part="GND4" gate="1" x="231.14" y="55.88"/>
+<instance part="IC10" gate="A" x="111.76" y="124.46"/>
+<instance part="IC8" gate="A" x="332.74" y="203.2"/>
+<instance part="P+1" gate="VCC" x="15.24" y="177.8"/>
+<instance part="P+9" gate="VCC" x="38.1" y="73.66"/>
+<instance part="P+10" gate="VCC" x="231.14" y="78.74"/>
+<instance part="IC3" gate="G$1" x="327.66" y="96.52"/>
+<instance part="GND5" gate="1" x="353.06" y="58.42"/>
+<instance part="P+2" gate="VCC" x="353.06" y="78.74"/>
+<instance part="IC4" gate="G$1" x="149.86" y="223.52"/>
+<instance part="IC6" gate="A" x="160.02" y="76.2"/>
+<instance part="IC7" gate="A" x="243.84" y="203.2"/>
+<instance part="P+5" gate="VCC" x="149.86" y="55.88"/>
+<instance part="GND11" gate="1" x="149.86" y="43.18"/>
+<instance part="CC3" gate="G$1" x="353.06" y="68.58"/>
+<instance part="CC9" gate="G$1" x="22.86" y="101.6"/>
+<instance part="CC8" gate="G$1" x="335.28" y="177.8"/>
+<instance part="CC5" gate="G$1" x="111.76" y="172.72"/>
+<instance part="P+7" gate="VCC" x="124.46" y="114.3"/>
+<instance part="P+12" gate="VCC" x="335.28" y="182.88"/>
+<instance part="P+13" gate="VCC" x="111.76" y="177.8"/>
+<instance part="P+14" gate="VCC" x="22.86" y="106.68"/>
+<instance part="GND12" gate="1" x="22.86" y="93.98"/>
+<instance part="GND14" gate="1" x="124.46" y="101.6"/>
+<instance part="GND17" gate="1" x="335.28" y="170.18"/>
+<instance part="GND18" gate="1" x="111.76" y="165.1"/>
+<instance part="CC6" gate="G$1" x="149.86" y="50.8"/>
+<instance part="CC10" gate="G$1" x="124.46" y="109.22"/>
+<instance part="IC2" gate="G$1" x="271.78" y="96.52"/>
+<instance part="GND7" gate="1" x="292.1" y="55.88"/>
+<instance part="P+6" gate="VCC" x="292.1" y="78.74"/>
+<instance part="CC2" gate="G$1" x="292.1" y="68.58"/>
+<instance part="IC5" gate="G$1" x="149.86" y="180.34"/>
+<instance part="P+11" gate="VCC" x="261.62" y="193.04"/>
+<instance part="GND16" gate="1" x="261.62" y="180.34"/>
+<instance part="CC7" gate="G$1" x="261.62" y="187.96"/>
+<instance part="S1" gate="BEF1" x="274.32" y="231.14" rot="MR270"/>
+<instance part="P+17" gate="VCC" x="266.7" y="241.3"/>
+<instance part="GND3" gate="1" x="218.44" y="203.2"/>
+<instance part="GND8" gate="1" x="317.5" y="185.42"/>
+<instance part="GND13" gate="1" x="129.54" y="73.66"/>
+<instance part="J1" gate="A" x="251.46" y="38.1" rot="R180"/>
+<instance part="IC9" gate="G$1" x="33.02" y="134.62"/>
+<instance part="P+3" gate="VCC" x="20.32" y="154.94"/>
+<instance part="GND6" gate="1" x="17.78" y="114.3"/>
+<instance part="P+15" gate="VCC" x="218.44" y="220.98"/>
+<instance part="P+4" gate="VCC" x="261.62" y="50.8"/>
+<instance part="GND9" gate="1" x="304.8" y="226.06"/>
+<instance part="J2" gate="G$1" x="335.28" y="243.84"/>
+<instance part="C1" gate="G$1" x="322.58" y="236.22"/>
+<instance part="GND10" gate="1" x="322.58" y="226.06"/>
+<instance part="IC11" gate="B" x="187.96" y="40.64"/>
+<instance part="IC11" gate="C" x="187.96" y="20.32"/>
+<instance part="Q1" gate="G$1" x="304.8" y="238.76"/>
+<instance part="CC1" gate="G$1" x="231.14" y="68.58"/>
+<instance part="P+16" gate="VCC" x="220.98" y="38.1"/>
+<instance part="GND15" gate="1" x="220.98" y="25.4"/>
+<instance part="CC11" gate="G$1" x="220.98" y="33.02"/>
+<instance part="IC11" gate="D" x="127" y="35.56"/>
+<instance part="IC11" gate="A" x="127" y="17.78"/>
+<instance part="GND19" gate="1" x="111.76" y="10.16"/>
+</instances>
+<busses>
+<bus name="D[0..7]">
+<segment>
+<wire x1="63.5" y1="190.5" x2="63.5" y2="137.16" width="0.762" layer="92"/>
+<wire x1="63.5" y1="137.16" x2="63.5" y2="104.14" width="0.762" layer="92"/>
+<wire x1="63.5" y1="104.14" x2="43.18" y2="104.14" width="0.762" layer="92"/>
+<wire x1="43.18" y1="104.14" x2="43.18" y2="53.34" width="0.762" layer="92"/>
+<wire x1="63.5" y1="137.16" x2="91.44" y2="137.16" width="0.762" layer="92"/>
+<wire x1="91.44" y1="137.16" x2="91.44" y2="119.38" width="0.762" layer="92"/>
+</segment>
+</bus>
+<bus name="A[0..15]">
+<segment>
+<wire x1="304.8" y1="149.86" x2="304.8" y2="215.9" width="0.762" layer="92"/>
+<wire x1="63.5" y1="195.58" x2="63.5" y2="233.68" width="0.762" layer="92"/>
+<wire x1="63.5" y1="195.58" x2="73.66" y2="195.58" width="0.762" layer="92"/>
+<wire x1="73.66" y1="195.58" x2="73.66" y2="149.86" width="0.762" layer="92"/>
+<wire x1="73.66" y1="149.86" x2="73.66" y2="96.52" width="0.762" layer="92"/>
+<wire x1="73.66" y1="96.52" x2="99.06" y2="96.52" width="0.762" layer="92"/>
+<wire x1="99.06" y1="96.52" x2="99.06" y2="63.5" width="0.762" layer="92"/>
+<wire x1="73.66" y1="96.52" x2="50.8" y2="96.52" width="0.762" layer="92"/>
+<wire x1="304.8" y1="149.86" x2="73.66" y2="149.86" width="0.762" layer="92"/>
+<wire x1="50.8" y1="96.52" x2="50.8" y2="86.36" width="0.762" layer="92"/>
+<label x="231.14" y="152.4" size="1.27" layer="95"/>
+</segment>
+</bus>
+<bus name="MA[0..8],A[9..12],MA[13..20]">
+<segment>
+<wire x1="182.88" y1="71.12" x2="182.88" y2="132.08" width="0.762" layer="92"/>
+<wire x1="182.88" y1="132.08" x2="304.8" y2="132.08" width="0.762" layer="92"/>
+<wire x1="304.8" y1="132.08" x2="304.8" y2="76.2" width="0.762" layer="92"/>
+<label x="363.22" y="160.02" size="1.27" layer="95" rot="R90"/>
+<wire x1="304.8" y1="132.08" x2="360.68" y2="132.08" width="0.762" layer="92"/>
+<wire x1="360.68" y1="132.08" x2="360.68" y2="215.9" width="0.762" layer="92"/>
+</segment>
+<segment>
+<wire x1="243.84" y1="76.2" x2="243.84" y2="132.08" width="0.762" layer="92"/>
+</segment>
+</bus>
+<bus name="MD[0..7]">
+<segment>
+<wire x1="228.6" y1="104.14" x2="228.6" y2="137.16" width="0.762" layer="92"/>
+<wire x1="228.6" y1="137.16" x2="345.44" y2="137.16" width="0.762" layer="92"/>
+<wire x1="345.44" y1="137.16" x2="345.44" y2="104.14" width="0.762" layer="92"/>
+<wire x1="228.6" y1="137.16" x2="223.52" y2="137.16" width="0.762" layer="92"/>
+<wire x1="223.52" y1="137.16" x2="139.7" y2="137.16" width="0.762" layer="92"/>
+<wire x1="139.7" y1="137.16" x2="132.08" y2="137.16" width="0.762" layer="92"/>
+<wire x1="132.08" y1="137.16" x2="132.08" y2="119.38" width="0.762" layer="92"/>
+<wire x1="139.7" y1="71.12" x2="139.7" y2="137.16" width="0.762" layer="92"/>
+<label x="220.98" y="157.48" size="1.27" layer="95" rot="R90"/>
+<label x="142.24" y="121.92" size="1.27" layer="95" rot="R90"/>
+<label x="149.86" y="139.7" size="1.27" layer="95"/>
+<wire x1="223.52" y1="213.36" x2="223.52" y2="137.16" width="0.762" layer="92"/>
+</segment>
+<segment>
+<wire x1="289.56" y1="104.14" x2="289.56" y2="137.16" width="0.762" layer="92"/>
+</segment>
+</bus>
+</busses>
+<nets>
+<net name="!NMI_SYS" class="0">
+<segment>
+<pinref part="J3A" gate="1" pin="17"/>
+<wire x1="60.96" y1="48.26" x2="55.88" y2="48.26" width="0.1524" layer="91"/>
+<label x="55.88" y="48.26" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="O7"/>
+<wire x1="162.56" y1="182.88" x2="167.64" y2="182.88" width="0.1524" layer="91"/>
+<label x="167.64" y="182.88" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="!MREQ_SYS" class="0">
+<segment>
+<pinref part="J3A" gate="1" pin="19"/>
+<wire x1="60.96" y1="43.18" x2="55.88" y2="43.18" width="0.1524" layer="91"/>
+<label x="55.88" y="43.18" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="O9"/>
+<wire x1="162.56" y1="231.14" x2="167.64" y2="231.14" width="0.1524" layer="91"/>
+<label x="167.64" y="231.14" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="D0" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="D0"/>
+<wire x1="58.42" y1="190.5" x2="63.5" y2="190.5" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3A" gate="1" pin="14"/>
+<wire x1="60.96" y1="55.88" x2="43.18" y2="55.88" width="0.1524" layer="91"/>
+<label x="45.72" y="56.515" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="A7"/>
+<wire x1="99.06" y1="121.92" x2="91.44" y2="121.92" width="0.1524" layer="91"/>
+<label x="93.98" y="121.92" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="D1" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="D1"/>
+<wire x1="58.42" y1="187.96" x2="63.5" y2="187.96" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3A" gate="1" pin="15"/>
+<wire x1="60.96" y1="53.34" x2="43.18" y2="53.34" width="0.1524" layer="91"/>
+<label x="45.72" y="53.975" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="A8"/>
+<wire x1="99.06" y1="119.38" x2="91.44" y2="119.38" width="0.1524" layer="91"/>
+<label x="93.98" y="119.38" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="D2" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="D2"/>
+<wire x1="58.42" y1="185.42" x2="63.5" y2="185.42" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3A" gate="1" pin="12"/>
+<wire x1="60.96" y1="60.96" x2="43.18" y2="60.96" width="0.1524" layer="91"/>
+<label x="45.72" y="61.595" size="1.27" layer="95"/>
+</segment>
+<segment>
+<wire x1="91.44" y1="132.08" x2="91.44" y2="129.54" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="A5"/>
+<wire x1="99.06" y1="127" x2="91.44" y2="127" width="0.1524" layer="91"/>
+<label x="93.98" y="127" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="D3" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="D3"/>
+<wire x1="58.42" y1="182.88" x2="63.5" y2="182.88" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3A" gate="1" pin="8"/>
+<wire x1="60.96" y1="71.12" x2="43.18" y2="71.12" width="0.1524" layer="91"/>
+<label x="45.72" y="71.755" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="A2"/>
+<wire x1="99.06" y1="134.62" x2="91.44" y2="134.62" width="0.1524" layer="91"/>
+<label x="93.98" y="134.62" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="D4" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="D4"/>
+<wire x1="58.42" y1="180.34" x2="63.5" y2="180.34" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3A" gate="1" pin="7"/>
+<wire x1="60.96" y1="73.66" x2="43.18" y2="73.66" width="0.1524" layer="91"/>
+<label x="45.72" y="74.295" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="A1"/>
+<wire x1="99.06" y1="137.16" x2="91.44" y2="137.16" width="0.1524" layer="91"/>
+<label x="93.98" y="137.16" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="D5" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="D5"/>
+<wire x1="58.42" y1="177.8" x2="63.5" y2="177.8" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3A" gate="1" pin="9"/>
+<wire x1="60.96" y1="68.58" x2="43.18" y2="68.58" width="0.1524" layer="91"/>
+<label x="45.72" y="69.215" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="A3"/>
+<wire x1="99.06" y1="132.08" x2="91.44" y2="132.08" width="0.1524" layer="91"/>
+<label x="93.98" y="132.08" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="D6" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="D6"/>
+<wire x1="58.42" y1="175.26" x2="63.5" y2="175.26" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3A" gate="1" pin="10"/>
+<wire x1="60.96" y1="66.04" x2="43.18" y2="66.04" width="0.1524" layer="91"/>
+<label x="45.72" y="66.675" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="A4"/>
+<wire x1="99.06" y1="129.54" x2="91.44" y2="129.54" width="0.1524" layer="91"/>
+<label x="93.98" y="129.54" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="D7" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="D7"/>
+<wire x1="58.42" y1="172.72" x2="63.5" y2="172.72" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3A" gate="1" pin="13"/>
+<wire x1="60.96" y1="58.42" x2="43.18" y2="58.42" width="0.1524" layer="91"/>
+<label x="45.72" y="59.055" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="A6"/>
+<wire x1="99.06" y1="124.46" x2="91.44" y2="124.46" width="0.1524" layer="91"/>
+<label x="93.98" y="124.46" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="A0" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A0"/>
+<wire x1="58.42" y1="233.68" x2="63.5" y2="233.68" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="10"/>
+<wire x1="88.9" y1="63.5" x2="99.06" y2="63.5" width="0.1524" layer="91"/>
+<label x="97.79" y="64.135" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="I2"/>
+<wire x1="137.16" y1="226.06" x2="132.08" y2="226.06" width="0.1524" layer="91"/>
+<label x="132.08" y="226.06" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="I5"/>
+<wire x1="22.86" y1="132.08" x2="17.78" y2="132.08" width="0.1524" layer="91"/>
+<label x="17.78" y="132.08" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="A1" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A1"/>
+<wire x1="58.42" y1="231.14" x2="63.5" y2="231.14" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="11"/>
+<wire x1="88.9" y1="66.04" x2="99.06" y2="66.04" width="0.1524" layer="91"/>
+<label x="97.79" y="66.675" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="I1"/>
+<wire x1="137.16" y1="228.6" x2="132.08" y2="228.6" width="0.1524" layer="91"/>
+<label x="132.08" y="228.6" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="I4"/>
+<wire x1="22.86" y1="134.62" x2="17.78" y2="134.62" width="0.1524" layer="91"/>
+<label x="17.78" y="134.62" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="A2" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A2"/>
+<wire x1="58.42" y1="228.6" x2="63.5" y2="228.6" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="12"/>
+<wire x1="88.9" y1="68.58" x2="99.06" y2="68.58" width="0.1524" layer="91"/>
+<label x="97.79" y="69.215" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="I3"/>
+<wire x1="22.86" y1="137.16" x2="17.78" y2="137.16" width="0.1524" layer="91"/>
+<label x="17.78" y="137.16" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I4"/>
+<wire x1="137.16" y1="177.8" x2="132.08" y2="177.8" width="0.1524" layer="91"/>
+<label x="132.08" y="177.8" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="A3" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A3"/>
+<wire x1="58.42" y1="226.06" x2="63.5" y2="226.06" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="13"/>
+<wire x1="88.9" y1="71.12" x2="99.06" y2="71.12" width="0.1524" layer="91"/>
+<label x="97.79" y="71.755" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I2"/>
+<wire x1="137.16" y1="182.88" x2="132.08" y2="182.88" width="0.1524" layer="91"/>
+<label x="132.08" y="182.88" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="A4" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A4"/>
+<wire x1="58.42" y1="223.52" x2="63.5" y2="223.52" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="14"/>
+<wire x1="88.9" y1="73.66" x2="99.06" y2="73.66" width="0.1524" layer="91"/>
+<label x="97.79" y="74.295" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="O0"/>
+<wire x1="162.56" y1="165.1" x2="167.64" y2="165.1" width="0.1524" layer="91"/>
+<label x="167.64" y="165.1" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="I3"/>
+<wire x1="137.16" y1="223.52" x2="132.08" y2="223.52" width="0.1524" layer="91"/>
+<label x="132.08" y="223.52" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="A5" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A5"/>
+<wire x1="58.42" y1="220.98" x2="63.5" y2="220.98" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="15"/>
+<wire x1="88.9" y1="76.2" x2="99.06" y2="76.2" width="0.1524" layer="91"/>
+<label x="97.79" y="76.835" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC8" gate="A" pin="1A"/>
+<wire x1="320.04" y1="215.9" x2="304.8" y2="215.9" width="0.1524" layer="91"/>
+<label x="307.34" y="215.9" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="A6" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A6"/>
+<wire x1="58.42" y1="218.44" x2="63.5" y2="218.44" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="16"/>
+<wire x1="88.9" y1="78.74" x2="99.06" y2="78.74" width="0.1524" layer="91"/>
+<label x="97.79" y="79.375" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC8" gate="A" pin="2A"/>
+<wire x1="320.04" y1="210.82" x2="304.8" y2="210.82" width="0.1524" layer="91"/>
+<label x="307.34" y="210.82" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="A7" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A7"/>
+<wire x1="58.42" y1="215.9" x2="63.5" y2="215.9" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="17"/>
+<wire x1="88.9" y1="81.28" x2="99.06" y2="81.28" width="0.1524" layer="91"/>
+<label x="97.79" y="81.915" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC8" gate="A" pin="4A"/>
+<wire x1="320.04" y1="200.66" x2="304.8" y2="200.66" width="0.1524" layer="91"/>
+<label x="307.34" y="200.66" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="A8" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A8"/>
+<wire x1="58.42" y1="213.36" x2="63.5" y2="213.36" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="18"/>
+<wire x1="88.9" y1="83.82" x2="99.06" y2="83.82" width="0.1524" layer="91"/>
+<label x="97.79" y="84.455" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC8" gate="A" pin="3A"/>
+<wire x1="320.04" y1="205.74" x2="304.8" y2="205.74" width="0.1524" layer="91"/>
+<label x="307.34" y="205.74" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="A9" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A9"/>
+<wire x1="58.42" y1="210.82" x2="63.5" y2="210.82" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="19"/>
+<wire x1="88.9" y1="86.36" x2="99.06" y2="86.36" width="0.1524" layer="91"/>
+<label x="97.79" y="86.995" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="A9"/>
+<wire x1="195.58" y1="99.06" x2="182.88" y2="99.06" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="99.06" x2="304.8" y2="99.06" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A9"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A9"/>
+<wire x1="256.54" y1="99.06" x2="243.84" y2="99.06" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="248.92" y1="149.86" x2="251.46" y2="149.86" width="0.1524" layer="91"/>
+<wire x1="251.46" y1="149.86" x2="251.46" y2="132.08" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="A10" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A10"/>
+<wire x1="58.42" y1="208.28" x2="63.5" y2="208.28" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="20"/>
+<wire x1="88.9" y1="88.9" x2="99.06" y2="88.9" width="0.1524" layer="91"/>
+<label x="97.79" y="89.535" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="A10"/>
+<wire x1="195.58" y1="96.52" x2="182.88" y2="96.52" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="96.52" x2="304.8" y2="96.52" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A10"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A10"/>
+<wire x1="256.54" y1="96.52" x2="243.84" y2="96.52" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="254" y1="149.86" x2="254" y2="132.08" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="A11" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A11"/>
+<wire x1="58.42" y1="205.74" x2="63.5" y2="205.74" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3A" gate="1" pin="1"/>
+<wire x1="60.96" y1="88.9" x2="50.8" y2="88.9" width="0.1524" layer="91"/>
+<label x="52.705" y="89.535" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="A11"/>
+<wire x1="195.58" y1="93.98" x2="182.88" y2="93.98" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="93.98" x2="304.8" y2="93.98" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A11"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A11"/>
+<wire x1="256.54" y1="93.98" x2="243.84" y2="93.98" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="256.54" y1="149.86" x2="256.54" y2="132.08" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="A12" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A12"/>
+<wire x1="58.42" y1="203.2" x2="63.5" y2="203.2" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J3A" gate="1" pin="2"/>
+<wire x1="60.96" y1="86.36" x2="50.8" y2="86.36" width="0.1524" layer="91"/>
+<label x="53.34" y="86.36" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="A12"/>
+<wire x1="195.58" y1="91.44" x2="182.88" y2="91.44" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="91.44" x2="304.8" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A12"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A12"/>
+<wire x1="256.54" y1="91.44" x2="243.84" y2="91.44" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="259.08" y1="149.86" x2="259.08" y2="132.08" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="A13" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A13"/>
+<wire x1="58.42" y1="200.66" x2="63.5" y2="200.66" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="CLK"/>
+<wire x1="22.86" y1="147.32" x2="17.78" y2="147.32" width="0.1524" layer="91"/>
+<label x="17.78" y="147.32" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="A14" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A14"/>
+<wire x1="58.42" y1="198.12" x2="63.5" y2="198.12" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="I1"/>
+<wire x1="22.86" y1="142.24" x2="17.78" y2="142.24" width="0.1524" layer="91"/>
+<label x="17.78" y="142.24" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="A15" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="A15"/>
+<wire x1="58.42" y1="195.58" x2="63.5" y2="195.58" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="I2"/>
+<wire x1="22.86" y1="139.7" x2="17.78" y2="139.7" width="0.1524" layer="91"/>
+<label x="17.78" y="139.7" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="!M1" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="M1"/>
+<wire x1="22.86" y1="233.68" x2="17.78" y2="233.68" width="0.1524" layer="91"/>
+<label x="17.78" y="233.68" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="7"/>
+<wire x1="88.9" y1="55.88" x2="93.98" y2="55.88" width="0.1524" layer="91"/>
+<label x="93.98" y="55.88" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I5"/>
+<wire x1="137.16" y1="175.26" x2="132.08" y2="175.26" width="0.1524" layer="91"/>
+<label x="132.08" y="175.26" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="!MREQ" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="MREQ"/>
+<wire x1="22.86" y1="231.14" x2="17.78" y2="231.14" width="0.1524" layer="91"/>
+<label x="17.78" y="231.14" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="I0"/>
+<wire x1="137.16" y1="231.14" x2="132.08" y2="231.14" width="0.1524" layer="91"/>
+<label x="132.08" y="231.14" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC11" gate="B" pin="I0"/>
+<wire x1="165.1" y1="43.18" x2="170.18" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="43.18" x2="175.26" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="43.18" x2="170.18" y2="38.1" width="0.1524" layer="91"/>
+<junction x="170.18" y="43.18"/>
+<pinref part="IC11" gate="C" pin="I0"/>
+<wire x1="170.18" y1="38.1" x2="170.18" y2="22.86" width="0.1524" layer="91"/>
+<wire x1="170.18" y1="22.86" x2="175.26" y2="22.86" width="0.1524" layer="91"/>
+<label x="165.1" y="43.18" size="1.27" layer="95" rot="R180" xref="yes"/>
+<pinref part="IC11" gate="B" pin="I1"/>
+<wire x1="175.26" y1="38.1" x2="170.18" y2="38.1" width="0.1524" layer="91"/>
+<junction x="170.18" y="38.1"/>
+</segment>
+</net>
+<net name="!IORQ" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="IORQ"/>
+<wire x1="22.86" y1="228.6" x2="17.78" y2="228.6" width="0.1524" layer="91"/>
+<label x="17.78" y="228.6" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I0"/>
+<wire x1="137.16" y1="187.96" x2="132.08" y2="187.96" width="0.1524" layer="91"/>
+<label x="132.08" y="187.96" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="!RD" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="RD"/>
+<wire x1="22.86" y1="226.06" x2="17.78" y2="226.06" width="0.1524" layer="91"/>
+<label x="17.78" y="226.06" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="1"/>
+<wire x1="88.9" y1="40.64" x2="93.98" y2="40.64" width="0.1524" layer="91"/>
+<label x="93.98" y="40.64" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="DIR"/>
+<wire x1="99.06" y1="114.3" x2="93.98" y2="114.3" width="0.1524" layer="91"/>
+<label x="93.98" y="114.3" size="1.27" layer="95" rot="MR0" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="I5"/>
+<wire x1="137.16" y1="218.44" x2="132.08" y2="218.44" width="0.1524" layer="91"/>
+<label x="132.08" y="218.44" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="!WR" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="WR"/>
+<wire x1="22.86" y1="223.52" x2="17.78" y2="223.52" width="0.1524" layer="91"/>
+<label x="17.78" y="223.52" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="2"/>
+<wire x1="88.9" y1="43.18" x2="93.98" y2="43.18" width="0.1524" layer="91"/>
+<label x="93.98" y="43.18" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="I4"/>
+<wire x1="137.16" y1="220.98" x2="132.08" y2="220.98" width="0.1524" layer="91"/>
+<label x="132.08" y="220.98" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="!RFSH" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="RFSH"/>
+<wire x1="22.86" y1="218.44" x2="17.78" y2="218.44" width="0.1524" layer="91"/>
+<label x="17.78" y="218.44" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="8"/>
+<wire x1="88.9" y1="58.42" x2="93.98" y2="58.42" width="0.1524" layer="91"/>
+<label x="93.98" y="58.42" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I6"/>
+<wire x1="137.16" y1="172.72" x2="132.08" y2="172.72" width="0.1524" layer="91"/>
+<label x="132.08" y="172.72" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="!HALT" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="HALT"/>
+<wire x1="22.86" y1="213.36" x2="17.78" y2="213.36" width="0.1524" layer="91"/>
+<label x="17.78" y="213.36" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="J3A" gate="1" pin="18"/>
+<wire x1="60.96" y1="45.72" x2="55.88" y2="45.72" width="0.1524" layer="91"/>
+<label x="55.88" y="45.72" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="!WAIT" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="WAIT"/>
+<wire x1="22.86" y1="208.28" x2="17.78" y2="208.28" width="0.1524" layer="91"/>
+<label x="17.78" y="208.28" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="4"/>
+<wire x1="88.9" y1="48.26" x2="93.98" y2="48.26" width="0.1524" layer="91"/>
+<label x="93.98" y="48.26" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="!INT" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="INT"/>
+<wire x1="22.86" y1="203.2" x2="17.78" y2="203.2" width="0.1524" layer="91"/>
+<label x="17.78" y="203.2" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="J3A" gate="1" pin="16"/>
+<wire x1="60.96" y1="50.8" x2="55.88" y2="50.8" width="0.1524" layer="91"/>
+<label x="55.88" y="50.8" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="O6"/>
+<wire x1="162.56" y1="180.34" x2="167.64" y2="180.34" width="0.1524" layer="91"/>
+<label x="167.64" y="180.34" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="!NMI" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="NMI"/>
+<wire x1="22.86" y1="200.66" x2="17.78" y2="200.66" width="0.1524" layer="91"/>
+<label x="17.78" y="200.66" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="O8"/>
+<wire x1="162.56" y1="185.42" x2="167.64" y2="185.42" width="0.1524" layer="91"/>
+<label x="167.64" y="185.42" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="!RESET" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="RESET"/>
+<wire x1="22.86" y1="195.58" x2="17.78" y2="195.58" width="0.1524" layer="91"/>
+<label x="17.78" y="195.58" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="6"/>
+<wire x1="88.9" y1="53.34" x2="93.98" y2="53.34" width="0.1524" layer="91"/>
+<label x="93.98" y="53.34" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC7" gate="A" pin="CLR"/>
+<wire x1="231.14" y1="190.5" x2="218.44" y2="190.5" width="0.1524" layer="91"/>
+<label x="218.44" y="190.5" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I3"/>
+<wire x1="137.16" y1="180.34" x2="132.08" y2="180.34" width="0.1524" layer="91"/>
+<label x="132.08" y="180.34" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="!BUSRQ" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="BUSRQ"/>
+<wire x1="22.86" y1="190.5" x2="17.78" y2="190.5" width="0.1524" layer="91"/>
+<label x="17.78" y="190.5" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="5"/>
+<wire x1="88.9" y1="50.8" x2="93.98" y2="50.8" width="0.1524" layer="91"/>
+<label x="93.98" y="50.8" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="!BUSAK" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="BUSAK"/>
+<wire x1="22.86" y1="187.96" x2="17.78" y2="187.96" width="0.1524" layer="91"/>
+<label x="17.78" y="187.96" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="J3B" gate="1" pin="3"/>
+<wire x1="88.9" y1="45.72" x2="93.98" y2="45.72" width="0.1524" layer="91"/>
+<label x="93.98" y="45.72" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="CLK" class="0">
+<segment>
+<pinref part="CPU" gate="1" pin="CLK"/>
+<wire x1="22.86" y1="182.88" x2="17.78" y2="182.88" width="0.1524" layer="91"/>
+<label x="17.78" y="182.88" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="J3A" gate="1" pin="6"/>
+<wire x1="60.96" y1="76.2" x2="55.88" y2="76.2" width="0.1524" layer="91"/>
+<label x="55.88" y="76.2" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="CLK/I0"/>
+<wire x1="137.16" y1="236.22" x2="132.08" y2="236.22" width="0.1524" layer="91"/>
+<label x="132.08" y="236.22" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="GND" class="1">
+<segment>
+<pinref part="GND1" gate="1" pin="GND"/>
+<wire x1="20.32" y1="170.18" x2="20.32" y2="177.8" width="0.1524" layer="91"/>
+<pinref part="CPU" gate="1" pin="GND"/>
+<wire x1="20.32" y1="177.8" x2="22.86" y2="177.8" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="GND2" gate="1" pin="GND"/>
+<wire x1="106.68" y1="55.88" x2="106.68" y2="60.96" width="0.1524" layer="91"/>
+<pinref part="J3B" gate="1" pin="9"/>
+<wire x1="88.9" y1="60.96" x2="106.68" y2="60.96" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="VSS"/>
+<pinref part="GND4" gate="1" pin="GND"/>
+<wire x1="223.52" y1="63.5" x2="231.14" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="63.5" x2="231.14" y2="58.42" width="0.1524" layer="91"/>
+<pinref part="CC1" gate="G$1" pin="2"/>
+<junction x="231.14" y="63.5"/>
+</segment>
+<segment>
+<pinref part="GND5" gate="1" pin="GND"/>
+<wire x1="353.06" y1="63.5" x2="353.06" y2="60.96" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="VSS"/>
+<wire x1="340.36" y1="63.5" x2="353.06" y2="63.5" width="0.1524" layer="91"/>
+<pinref part="CC3" gate="G$1" pin="2"/>
+<junction x="353.06" y="63.5"/>
+</segment>
+<segment>
+<pinref part="CC9" gate="G$1" pin="2"/>
+<pinref part="GND12" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="CC8" gate="G$1" pin="2"/>
+<pinref part="GND17" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="CC5" gate="G$1" pin="2"/>
+<pinref part="GND18" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="CC6" gate="G$1" pin="2"/>
+<pinref part="GND11" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="GND14" gate="1" pin="GND"/>
+<pinref part="CC10" gate="G$1" pin="2"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="VSS"/>
+<pinref part="GND7" gate="1" pin="GND"/>
+<wire x1="284.48" y1="63.5" x2="292.1" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="292.1" y1="63.5" x2="292.1" y2="58.42" width="0.1524" layer="91"/>
+<pinref part="CC2" gate="G$1" pin="2"/>
+<junction x="292.1" y="63.5"/>
+</segment>
+<segment>
+<pinref part="CC7" gate="G$1" pin="2"/>
+<pinref part="GND16" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="IC7" gate="A" pin="D3"/>
+<wire x1="231.14" y1="210.82" x2="218.44" y2="210.82" width="0.1524" layer="91"/>
+<pinref part="GND3" gate="1" pin="GND"/>
+<wire x1="218.44" y1="210.82" x2="218.44" y2="208.28" width="0.1524" layer="91"/>
+<pinref part="IC7" gate="A" pin="D4"/>
+<wire x1="218.44" y1="208.28" x2="218.44" y2="205.74" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="208.28" x2="218.44" y2="208.28" width="0.1524" layer="91"/>
+<junction x="218.44" y="208.28"/>
+</segment>
+<segment>
+<pinref part="IC8" gate="A" pin="G"/>
+<wire x1="320.04" y1="190.5" x2="317.5" y2="190.5" width="0.1524" layer="91"/>
+<pinref part="GND8" gate="1" pin="GND"/>
+<wire x1="317.5" y1="187.96" x2="317.5" y2="190.5" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC6" gate="A" pin="D5"/>
+<wire x1="147.32" y1="78.74" x2="129.54" y2="78.74" width="0.1524" layer="91"/>
+<pinref part="GND13" gate="1" pin="GND"/>
+<wire x1="129.54" y1="78.74" x2="129.54" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="129.54" y1="78.74" x2="129.54" y2="88.9" width="0.1524" layer="91"/>
+<junction x="129.54" y="78.74"/>
+<pinref part="IC6" gate="A" pin="D1"/>
+<wire x1="129.54" y1="88.9" x2="147.32" y2="88.9" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="GND"/>
+<wire x1="22.86" y1="119.38" x2="17.78" y2="119.38" width="0.1524" layer="91"/>
+<wire x1="17.78" y1="119.38" x2="17.78" y2="116.84" width="0.1524" layer="91"/>
+<pinref part="GND6" gate="1" pin="GND"/>
+<pinref part="IC9" gate="G$1" pin="I8"/>
+<wire x1="22.86" y1="124.46" x2="17.78" y2="124.46" width="0.1524" layer="91"/>
+<wire x1="17.78" y1="124.46" x2="17.78" y2="119.38" width="0.1524" layer="91"/>
+<junction x="17.78" y="119.38"/>
+</segment>
+<segment>
+<pinref part="GND10" gate="1" pin="GND"/>
+<pinref part="C1" gate="G$1" pin="2"/>
+<wire x1="322.58" y1="228.6" x2="322.58" y2="231.14" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="GND9" gate="1" pin="GND"/>
+<pinref part="Q1" gate="G$1" pin="S"/>
+</segment>
+<segment>
+<pinref part="CC11" gate="G$1" pin="2"/>
+<pinref part="GND15" gate="1" pin="GND"/>
+</segment>
+<segment>
+<pinref part="GND19" gate="1" pin="GND"/>
+<wire x1="111.76" y1="12.7" x2="111.76" y2="15.24" width="0.1524" layer="91"/>
+<pinref part="IC11" gate="D" pin="I0"/>
+<wire x1="111.76" y1="15.24" x2="111.76" y2="20.32" width="0.1524" layer="91"/>
+<wire x1="111.76" y1="20.32" x2="111.76" y2="33.02" width="0.1524" layer="91"/>
+<wire x1="111.76" y1="33.02" x2="111.76" y2="38.1" width="0.1524" layer="91"/>
+<wire x1="111.76" y1="38.1" x2="114.3" y2="38.1" width="0.1524" layer="91"/>
+<pinref part="IC11" gate="D" pin="I1"/>
+<wire x1="114.3" y1="33.02" x2="111.76" y2="33.02" width="0.1524" layer="91"/>
+<junction x="111.76" y="33.02"/>
+<pinref part="IC11" gate="A" pin="I0"/>
+<wire x1="114.3" y1="20.32" x2="111.76" y2="20.32" width="0.1524" layer="91"/>
+<junction x="111.76" y="20.32"/>
+<pinref part="IC11" gate="A" pin="I1"/>
+<wire x1="114.3" y1="15.24" x2="111.76" y2="15.24" width="0.1524" layer="91"/>
+<junction x="111.76" y="15.24"/>
+</segment>
+</net>
+<net name="VCC" class="1">
+<segment>
+<pinref part="CPU" gate="1" pin="VCC"/>
+<wire x1="22.86" y1="172.72" x2="15.24" y2="172.72" width="0.1524" layer="91"/>
+<wire x1="15.24" y1="172.72" x2="15.24" y2="175.26" width="0.1524" layer="91"/>
+<pinref part="P+1" gate="VCC" pin="VCC"/>
+</segment>
+<segment>
+<pinref part="J3A" gate="1" pin="11"/>
+<wire x1="60.96" y1="63.5" x2="38.1" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="38.1" y1="63.5" x2="38.1" y2="71.12" width="0.1524" layer="91"/>
+<pinref part="P+9" gate="VCC" pin="VCC"/>
+</segment>
+<segment>
+<pinref part="CC8" gate="G$1" pin="1"/>
+<pinref part="P+12" gate="VCC" pin="VCC"/>
+</segment>
+<segment>
+<pinref part="CC5" gate="G$1" pin="1"/>
+<pinref part="P+13" gate="VCC" pin="VCC"/>
+</segment>
+<segment>
+<pinref part="CC9" gate="G$1" pin="1"/>
+<pinref part="P+14" gate="VCC" pin="VCC"/>
+</segment>
+<segment>
+<pinref part="P+5" gate="VCC" pin="VCC"/>
+<pinref part="CC6" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<pinref part="CC3" gate="G$1" pin="1"/>
+<pinref part="P+2" gate="VCC" pin="VCC"/>
+<wire x1="353.06" y1="76.2" x2="353.06" y2="73.66" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="VCC"/>
+<wire x1="353.06" y1="73.66" x2="353.06" y2="71.12" width="0.1524" layer="91"/>
+<wire x1="340.36" y1="68.58" x2="342.9" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="342.9" y1="68.58" x2="342.9" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="342.9" y1="73.66" x2="353.06" y2="73.66" width="0.1524" layer="91"/>
+<junction x="353.06" y="73.66"/>
+</segment>
+<segment>
+<pinref part="IC1" gate="G$1" pin="VCC"/>
+<wire x1="223.52" y1="68.58" x2="226.06" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="68.58" x2="226.06" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="226.06" y1="73.66" x2="231.14" y2="73.66" width="0.1524" layer="91"/>
+<pinref part="P+10" gate="VCC" pin="VCC"/>
+<wire x1="231.14" y1="73.66" x2="231.14" y2="76.2" width="0.1524" layer="91"/>
+<pinref part="CC1" gate="G$1" pin="1"/>
+<wire x1="231.14" y1="71.12" x2="231.14" y2="73.66" width="0.1524" layer="91"/>
+<junction x="231.14" y="73.66"/>
+</segment>
+<segment>
+<pinref part="P+7" gate="VCC" pin="VCC"/>
+<pinref part="CC10" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="VCC"/>
+<wire x1="284.48" y1="68.58" x2="287.02" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="287.02" y1="68.58" x2="287.02" y2="73.66" width="0.1524" layer="91"/>
+<pinref part="CC2" gate="G$1" pin="1"/>
+<wire x1="287.02" y1="73.66" x2="292.1" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="292.1" y1="73.66" x2="292.1" y2="71.12" width="0.1524" layer="91"/>
+<pinref part="P+6" gate="VCC" pin="VCC"/>
+<wire x1="292.1" y1="73.66" x2="292.1" y2="76.2" width="0.1524" layer="91"/>
+<junction x="292.1" y="73.66"/>
+</segment>
+<segment>
+<pinref part="P+11" gate="VCC" pin="VCC"/>
+<pinref part="CC7" gate="G$1" pin="1"/>
+</segment>
+<segment>
+<pinref part="S1" gate="BEF1" pin="O"/>
+<wire x1="269.24" y1="233.68" x2="266.7" y2="233.68" width="0.1524" layer="91"/>
+<wire x1="266.7" y1="238.76" x2="266.7" y2="233.68" width="0.1524" layer="91"/>
+<pinref part="P+17" gate="VCC" pin="VCC"/>
+</segment>
+<segment>
+<pinref part="P+3" gate="VCC" pin="VCC"/>
+<wire x1="20.32" y1="149.86" x2="20.32" y2="152.4" width="0.1524" layer="91"/>
+<pinref part="IC9" gate="G$1" pin="VCC"/>
+<wire x1="22.86" y1="149.86" x2="20.32" y2="149.86" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="P+15" gate="VCC" pin="VCC"/>
+<pinref part="IC7" gate="A" pin="D1"/>
+<wire x1="218.44" y1="215.9" x2="218.44" y2="218.44" width="0.1524" layer="91"/>
+<wire x1="231.14" y1="215.9" x2="218.44" y2="215.9" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="J1" gate="A" pin="6"/>
+<pinref part="P+4" gate="VCC" pin="VCC"/>
+<wire x1="254" y1="43.18" x2="261.62" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="261.62" y1="43.18" x2="261.62" y2="48.26" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="P+16" gate="VCC" pin="VCC"/>
+<pinref part="CC11" gate="G$1" pin="1"/>
+</segment>
+</net>
+<net name="!IORQ_SYS" class="0">
+<segment>
+<pinref part="J3A" gate="1" pin="20"/>
+<wire x1="60.96" y1="40.64" x2="55.88" y2="40.64" width="0.1524" layer="91"/>
+<label x="55.88" y="40.64" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="O9"/>
+<wire x1="162.56" y1="187.96" x2="167.64" y2="187.96" width="0.1524" layer="91"/>
+<label x="167.64" y="187.96" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="!BUFEN" class="0">
+<segment>
+<pinref part="IC10" gate="A" pin="G"/>
+<wire x1="99.06" y1="111.76" x2="93.98" y2="111.76" width="0.1524" layer="91"/>
+<label x="93.98" y="111.76" size="1.27" layer="95" rot="MR0" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC8" gate="A" pin="!A!/B"/>
+<wire x1="320.04" y1="193.04" x2="314.96" y2="193.04" width="0.1524" layer="91"/>
+<label x="314.96" y="193.04" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="O2"/>
+<wire x1="162.56" y1="213.36" x2="167.64" y2="213.36" width="0.1524" layer="91"/>
+<label x="167.64" y="213.36" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I8"/>
+<wire x1="137.16" y1="167.64" x2="132.08" y2="167.64" width="0.1524" layer="91"/>
+<label x="132.08" y="167.64" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC11" gate="C" pin="I1"/>
+<wire x1="165.1" y1="17.78" x2="175.26" y2="17.78" width="0.1524" layer="91"/>
+<label x="165.1" y="17.78" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="MA18" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A18"/>
+<wire x1="195.58" y1="76.2" x2="182.88" y2="76.2" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC3" gate="G$1" pin="A18"/>
+<wire x1="312.42" y1="76.2" x2="304.8" y2="76.2" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A18"/>
+<wire x1="256.54" y1="76.2" x2="243.84" y2="76.2" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC6" gate="A" pin="Q8"/>
+<wire x1="172.72" y1="71.12" x2="182.88" y2="71.12" width="0.1524" layer="91"/>
+<label x="180.34" y="71.12" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="MA17" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A17"/>
+<wire x1="195.58" y1="78.74" x2="182.88" y2="78.74" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="78.74" x2="304.8" y2="78.74" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A17"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A17"/>
+<wire x1="256.54" y1="78.74" x2="243.84" y2="78.74" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC6" gate="A" pin="Q7"/>
+<wire x1="172.72" y1="73.66" x2="182.88" y2="73.66" width="0.1524" layer="91"/>
+<label x="180.34" y="73.66" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="MA16" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A16"/>
+<wire x1="195.58" y1="81.28" x2="182.88" y2="81.28" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="81.28" x2="304.8" y2="81.28" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A16"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A16"/>
+<wire x1="256.54" y1="81.28" x2="243.84" y2="81.28" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC6" gate="A" pin="Q6"/>
+<wire x1="172.72" y1="76.2" x2="182.88" y2="76.2" width="0.1524" layer="91"/>
+<label x="180.34" y="76.2" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="MA15" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A14"/>
+<wire x1="195.58" y1="86.36" x2="182.88" y2="86.36" width="0.1524" layer="91"/>
+<label x="185.42" y="86.36" size="1.27" layer="95"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="86.36" x2="304.8" y2="86.36" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A14"/>
+<label x="307.34" y="86.36" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A14"/>
+<wire x1="256.54" y1="86.36" x2="243.84" y2="86.36" width="0.1524" layer="91"/>
+<label x="246.38" y="86.36" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC6" gate="A" pin="Q3"/>
+<wire x1="172.72" y1="83.82" x2="182.88" y2="83.82" width="0.1524" layer="91"/>
+<label x="180.34" y="83.82" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="MA14" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A15"/>
+<wire x1="195.58" y1="83.82" x2="182.88" y2="83.82" width="0.1524" layer="91"/>
+<label x="185.42" y="83.82" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC6" gate="A" pin="Q2"/>
+<wire x1="172.72" y1="86.36" x2="182.88" y2="86.36" width="0.1524" layer="91"/>
+<label x="180.34" y="86.36" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A15"/>
+<wire x1="256.54" y1="83.82" x2="243.84" y2="83.82" width="0.1524" layer="91"/>
+<label x="246.38" y="83.82" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="J1" gate="A" pin="2"/>
+<wire x1="254" y1="33.02" x2="264.16" y2="33.02" width="0.1524" layer="91"/>
+<label x="264.16" y="33.02" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="MA13" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A13"/>
+<wire x1="182.88" y1="88.9" x2="195.58" y2="88.9" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="88.9" x2="304.8" y2="88.9" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A13"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A13"/>
+<wire x1="243.84" y1="88.9" x2="256.54" y2="88.9" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC6" gate="A" pin="Q4"/>
+<wire x1="172.72" y1="81.28" x2="182.88" y2="81.28" width="0.1524" layer="91"/>
+<label x="180.34" y="81.28" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="MA8" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A8"/>
+<wire x1="195.58" y1="101.6" x2="182.88" y2="101.6" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="101.6" x2="304.8" y2="101.6" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A8"/>
+</segment>
+<segment>
+<pinref part="IC8" gate="A" pin="3Y"/>
+<wire x1="345.44" y1="205.74" x2="360.68" y2="205.74" width="0.1524" layer="91"/>
+<label x="358.14" y="205.74" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A8"/>
+<wire x1="256.54" y1="101.6" x2="243.84" y2="101.6" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="MA7" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A7"/>
+<wire x1="195.58" y1="104.14" x2="182.88" y2="104.14" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="104.14" x2="304.8" y2="104.14" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A7"/>
+</segment>
+<segment>
+<pinref part="IC8" gate="A" pin="4Y"/>
+<wire x1="345.44" y1="200.66" x2="360.68" y2="200.66" width="0.1524" layer="91"/>
+<label x="358.14" y="200.66" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A7"/>
+<wire x1="256.54" y1="104.14" x2="243.84" y2="104.14" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="MA6" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A6"/>
+<wire x1="195.58" y1="106.68" x2="182.88" y2="106.68" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="106.68" x2="304.8" y2="106.68" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A6"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A6"/>
+<wire x1="256.54" y1="106.68" x2="243.84" y2="106.68" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC8" gate="A" pin="2Y"/>
+<wire x1="345.44" y1="210.82" x2="360.68" y2="210.82" width="0.1524" layer="91"/>
+<label x="358.14" y="210.82" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="MA5" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A5"/>
+<wire x1="195.58" y1="109.22" x2="182.88" y2="109.22" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="109.22" x2="304.8" y2="109.22" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A5"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A5"/>
+<wire x1="256.54" y1="109.22" x2="243.84" y2="109.22" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC8" gate="A" pin="1Y"/>
+<wire x1="345.44" y1="215.9" x2="360.68" y2="215.9" width="0.1524" layer="91"/>
+<label x="358.14" y="215.9" size="1.27" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="MA4" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A4"/>
+<wire x1="195.58" y1="111.76" x2="182.88" y2="111.76" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="111.76" x2="304.8" y2="111.76" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A4"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A4"/>
+<wire x1="256.54" y1="111.76" x2="243.84" y2="111.76" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="O0"/>
+<wire x1="162.56" y1="208.28" x2="167.64" y2="208.28" width="0.1524" layer="91"/>
+<label x="167.64" y="208.28" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="MA3" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A3"/>
+<wire x1="195.58" y1="114.3" x2="182.88" y2="114.3" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="114.3" x2="304.8" y2="114.3" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A3"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A3"/>
+<wire x1="256.54" y1="114.3" x2="243.84" y2="114.3" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="O4"/>
+<wire x1="162.56" y1="175.26" x2="167.64" y2="175.26" width="0.1524" layer="91"/>
+<label x="167.64" y="175.26" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="MA2" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A2"/>
+<wire x1="195.58" y1="116.84" x2="182.88" y2="116.84" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="116.84" x2="304.8" y2="116.84" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A2"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A2"/>
+<wire x1="256.54" y1="116.84" x2="243.84" y2="116.84" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="O4"/>
+<wire x1="43.18" y1="134.62" x2="48.26" y2="134.62" width="0.1524" layer="91"/>
+<label x="48.26" y="134.62" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="MA1" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A1"/>
+<wire x1="195.58" y1="119.38" x2="182.88" y2="119.38" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="119.38" x2="304.8" y2="119.38" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A1"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A1"/>
+<wire x1="256.54" y1="119.38" x2="243.84" y2="119.38" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="O5"/>
+<wire x1="43.18" y1="132.08" x2="48.26" y2="132.08" width="0.1524" layer="91"/>
+<label x="48.26" y="132.08" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="MA0" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="A0"/>
+<wire x1="195.58" y1="121.92" x2="182.88" y2="121.92" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="312.42" y1="121.92" x2="304.8" y2="121.92" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="A0"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="A0"/>
+<wire x1="256.54" y1="121.92" x2="243.84" y2="121.92" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="O6"/>
+<wire x1="43.18" y1="129.54" x2="48.26" y2="129.54" width="0.1524" layer="91"/>
+<label x="48.26" y="129.54" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="MD0" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="I/O0"/>
+<wire x1="223.52" y1="121.92" x2="228.6" y2="121.92" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="340.36" y1="121.92" x2="345.44" y2="121.92" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="I/O0"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="I/O0"/>
+<wire x1="284.48" y1="121.92" x2="289.56" y2="121.92" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="B7"/>
+<wire x1="124.46" y1="121.92" x2="132.08" y2="121.92" width="0.1524" layer="91"/>
+<label x="129.54" y="121.92" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC7" gate="A" pin="D5"/>
+<wire x1="231.14" y1="205.74" x2="223.52" y2="205.74" width="0.1524" layer="91"/>
+<label x="226.06" y="205.74" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC6" gate="A" pin="D4"/>
+<wire x1="147.32" y1="81.28" x2="139.7" y2="81.28" width="0.1524" layer="91"/>
+<label x="144.78" y="81.28" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="OE"/>
+<wire x1="43.18" y1="147.32" x2="48.26" y2="147.32" width="0.1524" layer="91"/>
+<label x="48.26" y="147.32" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="MD1" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="I/O1"/>
+<wire x1="223.52" y1="119.38" x2="228.6" y2="119.38" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="340.36" y1="119.38" x2="345.44" y2="119.38" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="I/O1"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="I/O1"/>
+<wire x1="284.48" y1="119.38" x2="289.56" y2="119.38" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="B8"/>
+<wire x1="124.46" y1="119.38" x2="132.08" y2="119.38" width="0.1524" layer="91"/>
+<label x="129.54" y="119.38" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC7" gate="A" pin="D6"/>
+<wire x1="231.14" y1="203.2" x2="223.52" y2="203.2" width="0.1524" layer="91"/>
+<label x="226.06" y="203.2" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC6" gate="A" pin="D2"/>
+<wire x1="147.32" y1="86.36" x2="139.7" y2="86.36" width="0.1524" layer="91"/>
+<label x="144.78" y="86.36" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="O8"/>
+<wire x1="43.18" y1="124.46" x2="48.26" y2="124.46" width="0.1524" layer="91"/>
+<label x="48.26" y="124.46" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="MD2" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="I/O2"/>
+<wire x1="223.52" y1="116.84" x2="228.6" y2="116.84" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="340.36" y1="116.84" x2="345.44" y2="116.84" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="I/O2"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="I/O2"/>
+<wire x1="284.48" y1="116.84" x2="289.56" y2="116.84" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="B5"/>
+<wire x1="124.46" y1="127" x2="132.08" y2="127" width="0.1524" layer="91"/>
+<label x="129.54" y="127" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC7" gate="A" pin="D7"/>
+<wire x1="231.14" y1="200.66" x2="223.52" y2="200.66" width="0.1524" layer="91"/>
+<label x="226.06" y="200.66" size="1.27" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC6" gate="A" pin="D3"/>
+<wire x1="147.32" y1="83.82" x2="139.7" y2="83.82" width="0.1524" layer="91"/>
+<label x="144.78" y="83.82" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="O7"/>
+<wire x1="43.18" y1="127" x2="48.26" y2="127" width="0.1524" layer="91"/>
+<label x="48.26" y="127" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="MD3" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="I/O3"/>
+<wire x1="223.52" y1="114.3" x2="228.6" y2="114.3" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="340.36" y1="114.3" x2="345.44" y2="114.3" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="I/O3"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="I/O3"/>
+<wire x1="284.48" y1="114.3" x2="289.56" y2="114.3" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC6" gate="A" pin="D6"/>
+<wire x1="147.32" y1="76.2" x2="139.7" y2="76.2" width="0.1524" layer="91"/>
+<label x="144.78" y="76.2" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="B2"/>
+<wire x1="124.46" y1="134.62" x2="132.08" y2="134.62" width="0.1524" layer="91"/>
+<label x="129.54" y="134.62" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC7" gate="A" pin="D8"/>
+<wire x1="231.14" y1="198.12" x2="223.52" y2="198.12" width="0.1524" layer="91"/>
+<label x="226.06" y="198.12" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="MD4" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="I/O4"/>
+<wire x1="223.52" y1="111.76" x2="228.6" y2="111.76" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="340.36" y1="111.76" x2="345.44" y2="111.76" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="I/O4"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="I/O4"/>
+<wire x1="284.48" y1="111.76" x2="289.56" y2="111.76" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC6" gate="A" pin="D7"/>
+<wire x1="147.32" y1="73.66" x2="139.7" y2="73.66" width="0.1524" layer="91"/>
+<label x="144.78" y="73.66" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="B1"/>
+<wire x1="124.46" y1="137.16" x2="132.08" y2="137.16" width="0.1524" layer="91"/>
+<label x="129.54" y="137.16" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<wire x1="137.16" y1="165.1" x2="132.08" y2="165.1" width="0.1524" layer="91"/>
+<label x="132.08" y="165.1" size="1.27" layer="95" rot="R180" xref="yes"/>
+<pinref part="IC5" gate="G$1" pin="I9"/>
+</segment>
+</net>
+<net name="MD5" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="I/O5"/>
+<wire x1="223.52" y1="109.22" x2="228.6" y2="109.22" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="340.36" y1="109.22" x2="345.44" y2="109.22" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="I/O5"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="I/O5"/>
+<wire x1="284.48" y1="109.22" x2="289.56" y2="109.22" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC6" gate="A" pin="D8"/>
+<wire x1="147.32" y1="71.12" x2="139.7" y2="71.12" width="0.1524" layer="91"/>
+<label x="144.78" y="71.12" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="B3"/>
+<wire x1="124.46" y1="132.08" x2="132.08" y2="132.08" width="0.1524" layer="91"/>
+<label x="129.54" y="132.08" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC7" gate="A" pin="D2"/>
+<wire x1="231.14" y1="213.36" x2="223.52" y2="213.36" width="0.1524" layer="91"/>
+<label x="226.06" y="213.36" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="MD6" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="I/O6"/>
+<wire x1="223.52" y1="106.68" x2="228.6" y2="106.68" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="340.36" y1="106.68" x2="345.44" y2="106.68" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="I/O6"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="I/O6"/>
+<wire x1="284.48" y1="106.68" x2="289.56" y2="106.68" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="I10"/>
+<wire x1="137.16" y1="205.74" x2="132.08" y2="205.74" width="0.1524" layer="91"/>
+<label x="132.08" y="205.74" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="B4"/>
+<wire x1="124.46" y1="129.54" x2="132.08" y2="129.54" width="0.1524" layer="91"/>
+<label x="129.54" y="129.54" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I7"/>
+<wire x1="137.16" y1="170.18" x2="132.08" y2="170.18" width="0.1524" layer="91"/>
+<label x="132.08" y="170.18" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="MD7" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="I/O7"/>
+<wire x1="223.52" y1="104.14" x2="228.6" y2="104.14" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<wire x1="340.36" y1="104.14" x2="345.44" y2="104.14" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="G$1" pin="I/O7"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="I/O7"/>
+<wire x1="284.48" y1="104.14" x2="289.56" y2="104.14" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC10" gate="A" pin="B6"/>
+<wire x1="124.46" y1="124.46" x2="132.08" y2="124.46" width="0.1524" layer="91"/>
+<label x="129.54" y="124.46" size="1.27" layer="95" rot="MR0"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I10"/>
+<wire x1="137.16" y1="162.56" x2="132.08" y2="162.56" width="0.1524" layer="91"/>
+<label x="132.08" y="162.56" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="I9"/>
+<wire x1="137.16" y1="208.28" x2="132.08" y2="208.28" width="0.1524" layer="91"/>
+<label x="132.08" y="208.28" size="1.27" layer="95" rot="MR0" xref="yes"/>
+</segment>
+</net>
+<net name="!ACLR" class="0">
+<segment>
+<pinref part="IC6" gate="A" pin="CLR"/>
+<wire x1="147.32" y1="63.5" x2="142.24" y2="63.5" width="0.1524" layer="91"/>
+<label x="142.24" y="63.5" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC11" gate="B" pin="O"/>
+<wire x1="200.66" y1="40.64" x2="205.74" y2="40.64" width="0.1524" layer="91"/>
+<label x="205.74" y="40.64" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="MAP1" class="0">
+<segment>
+<pinref part="IC7" gate="A" pin="Q6"/>
+<wire x1="256.54" y1="203.2" x2="284.48" y2="203.2" width="0.1524" layer="91"/>
+<pinref part="IC8" gate="A" pin="2B"/>
+<wire x1="320.04" y1="208.28" x2="284.48" y2="208.28" width="0.1524" layer="91"/>
+<wire x1="284.48" y1="208.28" x2="284.48" y2="203.2" width="0.1524" layer="91"/>
+<label x="307.34" y="208.28" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="MAP3" class="0">
+<segment>
+<pinref part="IC7" gate="A" pin="Q8"/>
+<wire x1="294.64" y1="198.12" x2="256.54" y2="198.12" width="0.1524" layer="91"/>
+<pinref part="IC8" gate="A" pin="3B"/>
+<wire x1="320.04" y1="203.2" x2="294.64" y2="203.2" width="0.1524" layer="91"/>
+<wire x1="294.64" y1="203.2" x2="294.64" y2="198.12" width="0.1524" layer="91"/>
+<label x="307.34" y="203.2" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="!BYPASS" class="0">
+<segment>
+<pinref part="IC5" gate="G$1" pin="O2"/>
+<wire x1="162.56" y1="170.18" x2="167.64" y2="170.18" width="0.1524" layer="91"/>
+<label x="167.64" y="170.18" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="I7"/>
+<wire x1="137.16" y1="213.36" x2="132.08" y2="213.36" width="0.1524" layer="91"/>
+<label x="132.08" y="213.36" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="I6"/>
+<wire x1="22.86" y1="129.54" x2="17.78" y2="129.54" width="0.1524" layer="91"/>
+<label x="17.78" y="129.54" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="MUXA" class="0">
+<segment>
+<pinref part="IC6" gate="A" pin="CLK"/>
+<wire x1="147.32" y1="66.04" x2="142.24" y2="66.04" width="0.1524" layer="91"/>
+<label x="142.24" y="66.04" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="I7"/>
+<wire x1="22.86" y1="127" x2="17.78" y2="127" width="0.1524" layer="91"/>
+<label x="17.78" y="127" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC11" gate="C" pin="O"/>
+<wire x1="200.66" y1="20.32" x2="205.74" y2="20.32" width="0.1524" layer="91"/>
+<label x="205.74" y="20.32" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="!CS0" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="!CS"/>
+<wire x1="195.58" y1="63.5" x2="190.5" y2="63.5" width="0.1524" layer="91"/>
+<label x="190.5" y="63.5" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="O4"/>
+<wire x1="162.56" y1="218.44" x2="167.64" y2="218.44" width="0.1524" layer="91"/>
+<label x="167.64" y="218.44" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="!CS1" class="0">
+<segment>
+<pinref part="IC2" gate="G$1" pin="!CS"/>
+<wire x1="256.54" y1="63.5" x2="251.46" y2="63.5" width="0.1524" layer="91"/>
+<label x="251.46" y="63.5" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="O5"/>
+<wire x1="162.56" y1="220.98" x2="167.64" y2="220.98" width="0.1524" layer="91"/>
+<label x="167.64" y="220.98" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="A13_SYS" class="0">
+<segment>
+<pinref part="J3A" gate="1" pin="3"/>
+<wire x1="60.96" y1="83.82" x2="55.88" y2="83.82" width="0.1524" layer="91"/>
+<label x="55.88" y="83.82" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="O1"/>
+<wire x1="43.18" y1="142.24" x2="48.26" y2="142.24" width="0.1524" layer="91"/>
+<label x="48.26" y="142.24" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="A14_SYS" class="0">
+<segment>
+<pinref part="J3A" gate="1" pin="4"/>
+<wire x1="60.96" y1="81.28" x2="55.88" y2="81.28" width="0.1524" layer="91"/>
+<label x="55.88" y="81.28" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="O2"/>
+<wire x1="43.18" y1="139.7" x2="48.26" y2="139.7" width="0.1524" layer="91"/>
+<label x="48.26" y="139.7" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="A15_SYS" class="0">
+<segment>
+<pinref part="J3A" gate="1" pin="5"/>
+<wire x1="60.96" y1="78.74" x2="55.88" y2="78.74" width="0.1524" layer="91"/>
+<label x="55.88" y="78.74" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC9" gate="G$1" pin="O3"/>
+<wire x1="43.18" y1="137.16" x2="48.26" y2="137.16" width="0.1524" layer="91"/>
+<label x="48.26" y="137.16" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="MAP0" class="0">
+<segment>
+<pinref part="IC7" gate="A" pin="Q5"/>
+<wire x1="256.54" y1="205.74" x2="281.94" y2="205.74" width="0.1524" layer="91"/>
+<pinref part="IC8" gate="A" pin="1B"/>
+<wire x1="320.04" y1="213.36" x2="281.94" y2="213.36" width="0.1524" layer="91"/>
+<wire x1="281.94" y1="213.36" x2="281.94" y2="205.74" width="0.1524" layer="91"/>
+<label x="307.34" y="213.36" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="!CS2" class="0">
+<segment>
+<pinref part="IC3" gate="G$1" pin="!CS"/>
+<label x="307.34" y="63.5" size="1.27" layer="95" rot="R180" xref="yes"/>
+<wire x1="312.42" y1="63.5" x2="307.34" y2="63.5" width="0.1524" layer="91"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="O6"/>
+<wire x1="162.56" y1="223.52" x2="167.64" y2="223.52" width="0.1524" layer="91"/>
+<label x="167.64" y="223.52" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="IC3_31" class="0">
+<segment>
+<pinref part="IC3" gate="G$1" pin="A15"/>
+<wire x1="312.42" y1="83.82" x2="302.26" y2="83.82" width="0.1524" layer="91"/>
+<label x="302.26" y="83.82" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="J1" gate="A" pin="5"/>
+<wire x1="254" y1="40.64" x2="261.62" y2="40.64" width="0.1524" layer="91"/>
+<label x="264.16" y="40.64" size="1.27" layer="95" xref="yes"/>
+<pinref part="J1" gate="A" pin="1"/>
+<wire x1="261.62" y1="40.64" x2="264.16" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="254" y1="30.48" x2="261.62" y2="30.48" width="0.1524" layer="91"/>
+<wire x1="261.62" y1="30.48" x2="261.62" y2="40.64" width="0.1524" layer="91"/>
+<junction x="261.62" y="40.64"/>
+</segment>
+</net>
+<net name="IC3_29" class="0">
+<segment>
+<pinref part="IC3" gate="G$1" pin="!WE"/>
+<wire x1="307.34" y1="68.58" x2="312.42" y2="68.58" width="0.1524" layer="91"/>
+<label x="307.34" y="68.58" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="J1" gate="A" pin="3"/>
+<wire x1="254" y1="35.56" x2="264.16" y2="35.56" width="0.1524" layer="91"/>
+<label x="264.16" y="35.56" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="!ROMMAP" class="0">
+<segment>
+<pinref part="IC5" gate="G$1" pin="O3"/>
+<wire x1="162.56" y1="172.72" x2="167.64" y2="172.72" width="0.1524" layer="91"/>
+<label x="167.64" y="172.72" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="I6"/>
+<wire x1="137.16" y1="215.9" x2="132.08" y2="215.9" width="0.1524" layer="91"/>
+<label x="132.08" y="215.9" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="!BOOT" class="0">
+<segment>
+<pinref part="S1" gate="BEF1" pin="P"/>
+<wire x1="279.4" y1="231.14" x2="281.94" y2="231.14" width="0.1524" layer="91"/>
+<label x="281.94" y="231.14" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I1"/>
+<wire x1="137.16" y1="185.42" x2="132.08" y2="185.42" width="0.1524" layer="91"/>
+<label x="132.08" y="185.42" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="!OE" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="!OE"/>
+<wire x1="195.58" y1="66.04" x2="190.5" y2="66.04" width="0.1524" layer="91"/>
+<label x="190.5" y="66.04" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="!OE"/>
+<wire x1="256.54" y1="66.04" x2="251.46" y2="66.04" width="0.1524" layer="91"/>
+<label x="251.46" y="66.04" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC3" gate="G$1" pin="!OE"/>
+<wire x1="312.42" y1="66.04" x2="307.34" y2="66.04" width="0.1524" layer="91"/>
+<label x="307.34" y="66.04" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="O7"/>
+<wire x1="162.56" y1="226.06" x2="167.64" y2="226.06" width="0.1524" layer="91"/>
+<label x="167.64" y="226.06" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="!WE" class="0">
+<segment>
+<pinref part="IC1" gate="G$1" pin="!WE"/>
+<wire x1="195.58" y1="68.58" x2="190.5" y2="68.58" width="0.1524" layer="91"/>
+<label x="190.5" y="68.58" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="G$1" pin="!WE"/>
+<wire x1="256.54" y1="68.58" x2="251.46" y2="68.58" width="0.1524" layer="91"/>
+<label x="251.46" y="68.58" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="O8"/>
+<wire x1="167.64" y1="228.6" x2="162.56" y2="228.6" width="0.1524" layer="91"/>
+<label x="167.64" y="228.6" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="J1" gate="A" pin="4"/>
+<wire x1="254" y1="38.1" x2="264.16" y2="38.1" width="0.1524" layer="91"/>
+<label x="264.16" y="38.1" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="!IOSEL" class="0">
+<segment>
+<pinref part="IC5" gate="G$1" pin="O1"/>
+<wire x1="162.56" y1="167.64" x2="167.64" y2="167.64" width="0.1524" layer="91"/>
+<label x="167.64" y="167.64" size="1.27" layer="95" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="I8"/>
+<wire x1="137.16" y1="210.82" x2="132.08" y2="210.82" width="0.1524" layer="91"/>
+<label x="132.08" y="210.82" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+</net>
+<net name="MAP2" class="0">
+<segment>
+<pinref part="IC7" gate="A" pin="Q7"/>
+<pinref part="IC8" gate="A" pin="4B"/>
+<wire x1="320.04" y1="198.12" x2="299.72" y2="198.12" width="0.1524" layer="91"/>
+<wire x1="299.72" y1="198.12" x2="299.72" y2="200.66" width="0.1524" layer="91"/>
+<wire x1="299.72" y1="200.66" x2="256.54" y2="200.66" width="0.1524" layer="91"/>
+<label x="307.34" y="198.12" size="1.27" layer="95"/>
+</segment>
+</net>
+<net name="INTDIS" class="0">
+<segment>
+<pinref part="IC5" gate="G$1" pin="O5"/>
+<wire x1="162.56" y1="177.8" x2="167.64" y2="177.8" width="0.1524" layer="91"/>
+<label x="167.64" y="177.8" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+<net name="!JUSTBOOTED" class="0">
+<segment>
+<pinref part="S1" gate="BEF1" pin="S"/>
+<wire x1="269.24" y1="228.6" x2="266.7" y2="228.6" width="0.1524" layer="91"/>
+<pinref part="IC7" gate="A" pin="Q1"/>
+<wire x1="256.54" y1="215.9" x2="266.7" y2="215.9" width="0.1524" layer="91"/>
+<wire x1="266.7" y1="215.9" x2="266.7" y2="228.6" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="MAPWR" class="0">
+<segment>
+<pinref part="IC5" gate="G$1" pin="CLK/I0"/>
+<wire x1="137.16" y1="193.04" x2="132.08" y2="193.04" width="0.1524" layer="91"/>
+<label x="132.08" y="193.04" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC7" gate="A" pin="CLK"/>
+<wire x1="231.14" y1="193.04" x2="218.44" y2="193.04" width="0.1524" layer="91"/>
+<label x="218.44" y="193.04" size="1.27" layer="95" rot="R180" xref="yes"/>
+</segment>
+<segment>
+<pinref part="IC4" gate="G$1" pin="O3"/>
+<label x="167.64" y="215.9" size="1.27" layer="95" xref="yes"/>
+<wire x1="165.1" y1="215.9" x2="167.64" y2="215.9" width="0.1524" layer="91"/>
+<wire x1="162.56" y1="215.9" x2="165.1" y2="215.9" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$1" class="0">
+<segment>
+<pinref part="IC7" gate="A" pin="Q2"/>
+<wire x1="256.54" y1="213.36" x2="276.86" y2="213.36" width="0.1524" layer="91"/>
+<wire x1="276.86" y1="213.36" x2="276.86" y2="220.98" width="0.1524" layer="91"/>
+<wire x1="276.86" y1="220.98" x2="294.64" y2="220.98" width="0.1524" layer="91"/>
+<pinref part="Q1" gate="G$1" pin="G"/>
+<wire x1="294.64" y1="220.98" x2="294.64" y2="236.22" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$2" class="0">
+<segment>
+<pinref part="J2" gate="G$1" pin="1"/>
+<pinref part="C1" gate="G$1" pin="1"/>
+<wire x1="322.58" y1="243.84" x2="332.74" y2="243.84" width="0.1524" layer="91"/>
+<wire x1="322.58" y1="238.76" x2="322.58" y2="243.84" width="0.1524" layer="91"/>
+<pinref part="Q1" gate="G$1" pin="D"/>
+<wire x1="304.8" y1="248.92" x2="304.8" y2="251.46" width="0.1524" layer="91"/>
+<wire x1="304.8" y1="251.46" x2="322.58" y2="251.46" width="0.1524" layer="91"/>
+<wire x1="322.58" y1="251.46" x2="322.58" y2="243.84" width="0.1524" layer="91"/>
+<junction x="322.58" y="243.84"/>
+</segment>
+</net>
+<net name="80/!40" class="0">
+<segment>
+<pinref part="IC4" gate="G$1" pin="O1"/>
+<wire x1="162.56" y1="210.82" x2="167.64" y2="210.82" width="0.1524" layer="91"/>
+<label x="167.64" y="210.82" size="1.27" layer="95" xref="yes"/>
+</segment>
+</net>
+</nets>
+</sheet>
+</sheets>
+<errors>
+<approved hash="104,1,223.52,63.5,IC1,VSS,GND,,,"/>
+<approved hash="104,1,340.36,63.5,IC3,VSS,GND,,,"/>
+<approved hash="104,1,284.48,63.5,IC2,VSS,GND,,,"/>
+<approved hash="106,1,162.56,177.8,INTDIS,,,,,"/>
+<approved hash="113,1,63.5423,63.3053,J3A,,,,,"/>
+<approved hash="113,1,86.3177,66.2347,J3B,,,,,"/>
+<approved hash="113,1,253.763,35.4288,J1,,,,,"/>
+<approved hash="113,1,332.977,245.241,J2,,,,,"/>
+</errors>
+</schematic>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+</compatibility>
+</eagle>
diff --git a/v1.2/bom.xlsx b/v1.2/bom.xlsx
new file mode 100644
index 0000000..3d34332
--- /dev/null
+++ b/v1.2/bom.xlsx
Binary files differ
diff --git a/v1.2/cam/jlcpcb-2layer.cam b/v1.2/cam/jlcpcb-2layer.cam
new file mode 120000
index 0000000..076f929
--- /dev/null
+++ b/v1.2/cam/jlcpcb-2layer.cam
@@ -0,0 +1 @@
+../../v1.1/cam/jlcpcb-2layer.cam \ No newline at end of file
diff --git a/v1.2/eagle.epf b/v1.2/eagle.epf
new file mode 100644
index 0000000..caa915b
--- /dev/null
+++ b/v1.2/eagle.epf
@@ -0,0 +1,559 @@
+[Eagle]
+Version="07 07 00"
+Platform="Linux"
+Serial="62191E841E-LSR-WLM-1EL"
+Globals="Globals"
+Desktop="Desktop"
+
+[Globals]
+AutoSaveProject=1
+UsedLibrary="/home/hpa/eagle/lbr/1284p.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/74ah.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/74xx-little-us.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/ESP8266-ESP12.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/SparkFun.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/advsocket-computer.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/altera-ep3c40f484.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/asix-v2.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/asix.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/atmel.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/atmel_prototype_header.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/attiny13.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/attiny24_44_84.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/avr-1.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/avr-2.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/avr-4.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/avr-5.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/avr-6.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/avr.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/bourns.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/cirrus-v1.0.2.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/clkgen-pll-hpa.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/commodore.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/con-amphenol-rj45-ld.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/con-din41612.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/con-lsta.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/con-lstb.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/con-molex-chiengineer.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/con-molex-picoblade.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/con-molex.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/con-pci_express(pci-e).lbr"
+UsedLibrary="/home/hpa/eagle/lbr/con-pulse.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/con-wieson.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/con-yamaichi-cf-2.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/con-yamaichi-cf.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/con-yamaichi.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/con_conec.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/controller-micro_atmel_jd.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/cy7c1009b.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/cypress-fx2.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/cypressledxx.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/cypresspsoc_0.30.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/dallas-rtc.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/dcdc.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/digi.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/dm9000.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/everlight.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/exar-sp207-213.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/ftdichip-4.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/hpa-idtqs.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/i2c-hpa.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/i2c.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/i2c_95xx.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/invensense-autosportlabs.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/l5973d.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/lasser.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/luminary-arm.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/max3238.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/maxim-dac.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/maxim-max1406.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/maxim.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/memory-atmel.lbr"
+UsedLibrary="/home/hpa/eagle/lbr/memory-bsi.lbr"
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+UsedLibrary="/opt/eagle-7.7.0/lbr/plcc-socket.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/pld-intel.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/plxtech.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/pot-vitrohm.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/pot-xicor.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/pot.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/ptc-ntc.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/quantum-research-group.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/rcl.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/recom-international.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/rectifier.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/ref-packages-longpad.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/ref-packages.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/relay.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/renesas.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/resistor-bourns.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/resistor-dil.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/resistor-net.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/resistor-power.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/resistor-ruf.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/resistor-shunt.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/resistor-sil.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/resistor.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/rf-micro-devices.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/rf-solutions.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/rohm.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/roundsolutions.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/semicon-smd-ipc.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/sensor-comus-group.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/sensor-heraeus.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/sensor-infratec.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/sharp.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/silabs.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/sim-technology.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/sipex.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/smd-ipc.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/smd-special.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/solomon-systech.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/solpad.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/speaker.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/special-drill.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/special.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/st-microelectronics.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/stm32xx.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/supertex.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/supply1.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/supply2.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/switch-alps.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/switch-coto.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/switch-dil.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/switch-misc.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/switch-omron.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/switch-raychem.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/switch-reed.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/switch.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/telcom.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/telecontrolli.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/telefunken.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/test-mate.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/testpad.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/texas-sn55-sn75.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/texas.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/toshiba.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/traco-electronic.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/trafo-bei.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/trafo-hammondmfg.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/trafo-siemens.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/trafo-xicon.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/trafo.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/transformer-pulse.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/transistor-fet.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/transistor-neu-to92.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/transistor-npn.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/transistor-pnp.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/transistor-power.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/transistor-small-signal.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/transistor.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/triac.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/trimble.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/tripas.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/u-blox.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/uln-udn.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/v-reg-micrel.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/v-reg.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/varistor.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/wafer-scale-psd.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/wirepad.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/xicor.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/xilinx-virtex-v5.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/xilinx-xc18v.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/xilinx-xc9.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/xilinx-xcv.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/zetex.lbr"
+UsedLibrary="/opt/eagle-7.7.0/lbr/zilog.lbr"
+
+[Win_1]
+Type="Control Panel"
+Loc="0 0 1919 2100"
+State=2
+Number=0
+
+[Win_2]
+Type="Schematic Editor"
+Loc="0 0 2539 2140"
+State=2
+Number=1
+File="abc80-1m-sram.sch"
+View="-8.29656 -5.80736 396.709 269.759"
+WireWidths=" 0 0.3048 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0.4064 0.1524"
+PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
+PadDrills=" 0.5 0.6 0.7 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.8"
+ViaDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
+ViaDrills=" 0.5 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.6"
+HoleDrills=" 0.5 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.6"
+TextSizes=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.778"
+PolygonSpacings=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.27"
+PolygonIsolates=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
+MiterRadiuss=" 0.254 0.3175 0.635 1.27 2.54 1 2 2.5 5 7.5 10 0"
+DimensionWidths=" 0 0.127 0.254 0.1 0.26 0.13"
+DimensionExtWidths=" 0.127 0.254 0.1 0.13 0.26 0"
+DimensionExtLengths=" 1.27 2.54 1 2 3 0"
+DimensionExtOffsets=" 1.27 2.54 1 2 3 0"
+SmdSizes=" 0.3048 0.1524 0.4064 0.2032 0.6096 0.3048 0.8128 0.4064 1.016 0.508 1.27 0.6604 1.4224 0.7112 1.6764 0.8128 1.778 0.9144 1.9304 0.9652 2.1844 1.0668 2.54 1.27 3.81 1.9304 5.08 2.54 6.4516 3.2512 1.27 0.635"
+WireBend=0
+WireBendSet=31
+WireCap=1
+MiterStyle=0
+PadShape=0
+ViaShape=0
+PolygonPour=0
+PolygonRank=0
+PolygonThermals=1
+PolygonOrphans=0
+TextRatio=8
+DimensionUnit=1
+DimensionPrecision=2
+DimensionShowUnit=0
+PinDirection=3
+PinFunction=0
+PinLength=2
+PinVisible=3
+SwapLevel=0
+ArcDirection=0
+AddLevel=2
+PadsSameType=0
+Layer=91
+Sheet="1"
+
+[Win_3]
+Type="Board Editor"
+Loc="1223 123 3419 1689"
+State=2
+Number=2
+File="abc80-1m-sram.brd"
+View="-6.20776 -6.83768 105.268 84.5617"
+WireWidths=" 0 0.254 0.3048 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0.4064"
+PadDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
+PadDrills=" 0.5 0.6 0.7 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.8"
+ViaDiameters=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
+ViaDrills=" 0.5 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.6"
+HoleDrills=" 0.5 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.2 2.8 3.2 0.6"
+TextSizes=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.778"
+PolygonSpacings=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 5.08 6.4516 1.27"
+PolygonIsolates=" 0.254 0.3048 0.4064 0.6096 0.8128 1.016 1.27 1.4224 1.6764 1.778 1.9304 2.1844 2.54 3.81 6.4516 0"
+MiterRadiuss=" 0.254 0.3175 0.635 1.27 2.54 1 2 2.5 5 7.5 10 0"
+DimensionWidths=" 0 0.127 0.254 0.1 0.26 0.13"
+DimensionExtWidths=" 0.127 0.254 0.1 0.13 0.26 0"
+DimensionExtLengths=" 1.27 2.54 1 2 3 0"
+DimensionExtOffsets=" 1.27 2.54 1 2 3 0"
+SmdSizes=" 0.3048 0.1524 0.4064 0.2032 0.6096 0.3048 0.8128 0.4064 1.016 0.508 1.27 0.6604 1.4224 0.7112 1.6764 0.8128 1.778 0.9144 1.9304 0.9652 2.1844 1.0668 2.54 1.27 3.81 1.9304 5.08 2.54 6.4516 3.2512 1.27 0.635"
+WireBend=0
+WireBendSet=0
+WireCap=1
+MiterStyle=0
+PadShape=0
+ViaShape=0
+PolygonPour=0
+PolygonRank=1
+PolygonThermals=1
+PolygonOrphans=0
+TextRatio=8
+DimensionUnit=1
+DimensionPrecision=2
+DimensionShowUnit=0
+PinDirection=3
+PinFunction=0
+PinLength=2
+PinVisible=3
+SwapLevel=0
+ArcDirection=0
+AddLevel=2
+PadsSameType=0
+Layer=43
+
+[Desktop]
+Screen="3840 2160"
+Window="Win_1"
+Window="Win_2"
+Window="Win_3"
diff --git a/v1.2/pld/Makefile b/v1.2/pld/Makefile
new file mode 100644
index 0000000..5e183a3
--- /dev/null
+++ b/v1.2/pld/Makefile
@@ -0,0 +1,11 @@
+MAKEFLAGS := -Rr
+
+CC = cc
+CPPFLAGS = -x assembler-with-cpp -undef -P
+
+.SUFFIXES:
+.SUFFIXES: .pld .pldi
+
+%.pldi: %.pld
+ $(CC) $(CPPFLAGS) -E -o $@ $<
+
diff --git a/v1.2/pld/abc80-1m-ic4.abs b/v1.2/pld/abc80-1m-ic4.abs
new file mode 100644
index 0000000..10a82d9
--- /dev/null
+++ b/v1.2/pld/abc80-1m-ic4.abs
Binary files differ
diff --git a/v1.2/pld/abc80-1m-ic4.doc b/v1.2/pld/abc80-1m-ic4.doc
new file mode 100644
index 0000000..8eed7ae
--- /dev/null
+++ b/v1.2/pld/abc80-1m-ic4.doc
@@ -0,0 +1,395 @@
+
+*******************************************************************************
+ abc80-1m-ic4
+*******************************************************************************
+
+CUPL(WM) 5.0a Serial# 60008009
+Device g22v10 Library DLIB-h-40-1
+Created Sun Jan 24 16:30:45 2021
+Name abc80-1m-ic4
+Partno 04
+Revision 1.2.0
+Date 2021-01-24
+Designer H. Peter Anvin
+Company Self
+Assembly abc80-1m-sram
+Location IC4
+
+===============================================================================
+ Expanded Product Terms
+===============================================================================
+
+BUFEN.d =>
+ A0 & A1 & !IOSELn & !WRn
+ # BYPASSn & !MD7 & !MREQn
+ # BYPASSn & !MD6 & !MREQn
+ # A4 & !IOSELn
+ # BUFEN & !MREQn
+ # BUFEN & !IOSELn
+
+BUFEN.ar =>
+ 0
+
+CS0.d =>
+ !BUFEN & BYPASSn & !MD6 & !MD7 & !MREQn
+ # !A0 & !A1 & A4 & BUFEN & !IOSELn & !WRn
+ # A0 & A1 & A4 & BUFEN & !IOSELn & !WRn
+ # !A0 & !A1 & A4 & !IOSELn & !RDn
+ # A0 & A1 & A4 & !IOSELn & !RDn
+ # IOSELn & MREQn & ROMMAPn
+ # BUFEN & CS0 & !MREQn
+
+CS0.ar =>
+ 0
+
+CS1.d =>
+ !BUFEN & BYPASSn & MD6 & !MD7 & !MREQn
+ # A0 & !A1 & A4 & BUFEN & !IOSELn & !WRn
+ # A0 & !A1 & A4 & !IOSELn & !RDn
+ # BUFEN & CS1 & !MREQn
+
+CS1.ar =>
+ 0
+
+CS2.d =>
+ !A0 & A1 & A4 & BUFEN & !IOSELn & !WRn
+ # !BUFEN & BYPASSn & !MD6 & MD7 & !MREQn
+ # !A0 & A1 & A4 & !IOSELn & !RDn
+ # IOSELn & MREQn & !ROMMAPn
+ # BUFEN & CS2 & !MREQn
+
+CS2.ar =>
+ 0
+
+MA4 =>
+ A4 & BUFEN & !MREQn
+ # MREQn & TKN80EN
+ # !BUFEN & TKN80EN
+
+MAPWR.d =>
+ A0 & A1 & BUFEN & !IOSELn & !WRn
+
+MAPWR.ar =>
+ 0
+
+MREQ_SYS =>
+ !BUFEN & MD6 & MD7 & !MREQn
+ # !BUFEN & !BYPASSn & !MREQn
+
+OEn =>
+ BUFEN & IOSELn & MREQn
+ # !A4 & BUFEN & MREQn
+ # BUFEN & RDn
+
+TKN80EN.d =>
+ !A0 & !A1 & !A4 & IOSELn & MREQn & !RDn
+ # RDn & TKN80EN
+ # !MREQn & TKN80EN
+ # A4 & TKN80EN
+ # IOSELn & TKN80EN
+ # !A1 & TKN80EN
+ # !A0 & TKN80EN
+
+TKN80EN.ar =>
+ 0
+
+WE =>
+ A4 & BUFEN & !IOSELn & !WRn
+ # BUFEN & !MREQn & !WRn
+
+ctlio =>
+ A0 & A1 & !IOSELn & !WRn
+
+false =>
+ 0
+
+mapio =>
+ A4 & !IOSELn
+
+muxa =>
+ BUFEN & !MREQn
+
+ourmem =>
+ BYPASSn & !MD6 & !MREQn
+ # BYPASSn & !MD7 & !MREQn
+
+system =>
+ !BYPASSn
+ # MD6 & MD7
+
+true =>
+ 1
+
+BUFEN.oe =>
+ 1
+
+CS0.oe =>
+ 1
+
+CS1.oe =>
+ 1
+
+CS2.oe =>
+ 1
+
+MA4.oe =>
+ 1
+
+MAPWR.oe =>
+ 1
+
+MREQ_SYS.oe =>
+ 1
+
+OEn.oe =>
+ 1
+
+TKN80EN.oe =>
+ 1
+
+WE.oe =>
+ 1
+
+
+===============================================================================
+ Symbol Table
+===============================================================================
+
+Pin Variable Pterms Max Min
+Pol Name Ext Pin Type Used Pterms Level
+--- -------- --- --- ---- ------ ------ -----
+
+ A0 4 V - - -
+ A1 3 V - - -
+ A4 5 V - - -
+ ! BUFEN 16 V - - -
+ ! BUFEN d 16 X 6 12 4
+ BUFEN ar 16 X 1 1 1
+ BYPASSn 9 V - - -
+ CLK 1 V - - -
+ ! CS0 18 V - - -
+ ! CS0 d 18 X 7 16 4
+ CS0 ar 18 X 1 1 1
+ ! CS1 19 V - - -
+ ! CS1 d 19 X 4 16 4
+ CS1 ar 19 X 1 1 1
+ ! CS2 20 V - - -
+ ! CS2 d 20 X 5 14 4
+ CS2 ar 20 X 1 1 1
+ IOSELn 10 V - - -
+ MA4 14 V 3 8 4
+ MAPWR 17 V - - -
+ MAPWR d 17 X 1 14 4
+ MAPWR ar 17 X 1 1 1
+ MD6 13 V - - -
+ MD7 11 V - - -
+ ! MREQ_SYS 23 V 2 8 4
+ MREQn 2 V - - -
+ OEn 21 V 3 12 4
+ RDn 7 V - - -
+ ROMMAPn 8 V - - -
+ TKN80EN 15 V - - -
+ TKN80EN d 15 X 7 10 4
+ TKN80EN ar 15 X 1 1 1
+ ! WE 22 V 2 10 4
+ WRn 6 V - - -
+ ctlio 0 I 1 - -
+ false 0 I 1 - -
+ mapio 0 I 1 - -
+ muxa 0 I 1 - -
+ ourmem 0 I 2 - -
+ system 0 I 2 - -
+ true 0 I 1 - -
+ BUFEN oe 16 D 1 1 0
+ CS0 oe 18 D 1 1 0
+ CS1 oe 19 D 1 1 0
+ CS2 oe 20 D 1 1 0
+ MA4 oe 14 D 1 1 0
+ MAPWR oe 17 D 1 1 0
+ MREQ_SYS oe 23 D 1 1 0
+ OEn oe 21 D 1 1 0
+ TKN80EN oe 15 D 1 1 0
+ WE oe 22 D 1 1 0
+
+
+LEGEND D : default variable F : field G : group
+ I : intermediate variable N : node M : extended node
+ U : undefined V : variable X : extended variable
+ T : function
+
+
+===============================================================================
+ Fuse Plot
+===============================================================================
+
+SP
+ 05764 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+
+AR
+ 00000 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+
+Pin #23 05808 Mode x-
+ 00044 --------------------------------------------
+ 00088 -----x------------------------x---------x-x-
+ 00132 -----x------------------------x--x----------
+ 00176 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00220 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00264 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00308 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00352 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00396 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #22 05810 Mode x-
+ 00440 --------------------------------------------
+ 00484 ----------------x----x---------x-----x------
+ 00528 -----x---------------x---------x------------
+ 00572 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00616 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00660 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00704 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00748 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00792 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00836 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00880 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #21 05812 Mode --
+ 00924 --------------------------------------------
+ 00968 ----x--------------------------x----x-------
+ 01012 ----x------------x-------------x------------
+ 01056 ------------------------x------x------------
+ 01100 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01144 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01188 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01232 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01276 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01320 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01364 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01408 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01452 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #20 05814 Mode xx
+ 01496 --------------------------------------------
+ 01540 --------x----x--x----x---------x-----x------
+ 01584 -----x------------------------x-x-------x--x
+ 01628 --------x----x--x--------x-----------x------
+ 01672 ----x------------------------x------x-------
+ 01716 -----x---------x---------------x------------
+ 01760 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01804 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01848 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01892 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01936 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01980 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02024 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02068 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02112 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #19 05816 Mode xx
+ 02156 --------------------------------------------
+ 02200 -----x------------------------x-x--------xx-
+ 02244 ---------x--x---x----x---------x-----x------
+ 02288 ---------x--x---x--------x-----------x------
+ 02332 -----x-------------x-----------x------------
+ 02376 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02420 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02464 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02508 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02552 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02596 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02640 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02684 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02728 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02772 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02816 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02860 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #18 05818 Mode xx
+ 02904 --------------------------------------------
+ 02948 -----x------------------------x-x--------x-x
+ 02992 ---------x---x--x----x---------x-----x------
+ 03036 --------x---x---x----x---------x-----x------
+ 03080 ---------x---x--x--------x-----------x------
+ 03124 --------x---x---x--------x-----------x------
+ 03168 ----x-----------------------x-------x-------
+ 03212 -----x-----------------x-------x------------
+ 03256 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03300 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03344 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03388 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03432 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03476 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03520 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03564 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03608 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #17 05820 Mode -x
+ 03652 --------------------------------------------
+ 03696 --------x---x--------x---------x-----x------
+ 03740 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03784 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03828 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03872 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03916 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03960 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04004 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04048 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04092 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04136 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04180 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04224 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04268 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #16 05822 Mode xx
+ 04312 --------------------------------------------
+ 04356 --------x---x--------x---------------x------
+ 04400 -----x--------------------------x--------x--
+ 04444 -----x--------------------------x----------x
+ 04488 ----------------x--------------------x------
+ 04532 -----x-------------------------x------------
+ 04576 -------------------------------x-----x------
+ 04620 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04664 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04708 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04752 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04796 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04840 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #15 05824 Mode -x
+ 04884 --------------------------------------------
+ 04928 ----x----x---x---x-------x----------x-------
+ 04972 ------------------------x----------x--------
+ 05016 -----x-----------------------------x--------
+ 05060 ----------------x------------------x--------
+ 05104 -----------------------------------xx-------
+ 05148 ---------x-------------------------x--------
+ 05192 -------------x---------------------x--------
+ 05236 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05280 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05324 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #14 05826 Mode --
+ 05368 --------------------------------------------
+ 05412 -----x----------x--------------x------------
+ 05456 ----x------------------------------x--------
+ 05500 ------------------------------x----x--------
+ 05544 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05588 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05632 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05676 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05720 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+
+
+LEGEND X : fuse not blown
+ - : fuse blown
+
+===============================================================================
+ Chip Diagram
+===============================================================================
+
+ ______________
+ | abc80-1m-ic4 |
+ CLK x---|1 24|---x Vcc
+ MREQn x---|2 23|---x !MREQ_SYS
+ A1 x---|3 22|---x !WE
+ A0 x---|4 21|---x OEn
+ A4 x---|5 20|---x !CS2
+ WRn x---|6 19|---x !CS1
+ RDn x---|7 18|---x !CS0
+ ROMMAPn x---|8 17|---x MAPWR
+ BYPASSn x---|9 16|---x !BUFEN
+ IOSELn x---|10 15|---x TKN80EN
+ MD7 x---|11 14|---x MA4
+ GND x---|12 13|---x MD6
+ |______________|
+
diff --git a/v1.2/pld/abc80-1m-ic4.jed b/v1.2/pld/abc80-1m-ic4.jed
new file mode 100644
index 0000000..bfbabb0
--- /dev/null
+++ b/v1.2/pld/abc80-1m-ic4.jed
@@ -0,0 +1,99 @@
+
+CUPL(WM) 5.0a Serial# 60008009
+Device g22v10 Library DLIB-h-40-1
+Created Sun Jan 24 16:30:45 2021
+Name abc80-1m-ic4
+Partno 04
+Revision 1.2.0
+Date 2021-01-24
+Designer H. Peter Anvin
+Company Self
+Assembly abc80-1m-sram
+Location IC4
+*QP24
+*QF5892
+*G0
+*F0
+*L00032 00000000000011111111111111111111
+*L00064 11111111111111111111111111111011
+*L00096 11111111111111111111110111111111
+*L00128 01011111101111111111111111111111
+*L00160 11011011111111110000000000000000
+*L00416 00000000000000000000000011111111
+*L00448 11111111111111111111111111111111
+*L00480 11111111111111111111011110111111
+*L00512 11101111101111111111101111111111
+*L00544 11111011111111101111111111110000
+*L00896 00000000000000000000000000001111
+*L00928 11111111111111111111111111111111
+*L00960 11111111111101111111111111111111
+*L00992 11111110111101111111111101111111
+*L01024 11111011111111111110111111111111
+*L01056 11111111111111111111111101111110
+*L01088 11111111111100000000000000000000
+*L01472 00000000000000000000000011111111
+*L01504 11111111111111111111111111111111
+*L01536 11111111111101111011011110111111
+*L01568 11101111101111111111101111111111
+*L01600 11111111111111010111111101101111
+*L01632 11110111101101111111101111111111
+*L01664 10111111111101111111111111111111
+*L01696 11111011111101111111111110111111
+*L01728 11101111111111111110111111111111
+*L02144 00000000000011111111111111111111
+*L02176 11111111111111111111111111111011
+*L02208 11111111111111111111110101111111
+*L02240 10011111111110110111011110111111
+*L02272 11101111101111111111111110110111
+*L02304 01111111101111111111101111111111
+*L02336 10111111111111101111111111101111
+*L02368 11111111000000000000000000000000
+*L02880 00000000000000000000000011111111
+*L02912 11111111111111111111111111111111
+*L02944 11111111101111111111111111111111
+*L02976 11010111111110101111111110111011
+*L03008 01111011111111101111101111111111
+*L03040 11110111011101111011111111101111
+*L03072 10111111111111111011101101111111
+*L03104 10111111111110111111111111110111
+*L03136 01110111111110111111111110111111
+*L03168 11110111111111111111111111110111
+*L03200 11110111111111111011111111111111
+*L03232 11101111111011111111111100000000
+*L03648 00001111111111111111111111111111
+*L03680 11111111111111111111111101110111
+*L03712 11111011111111101111101111110000
+*L04288 00000000000000000000000011111111
+*L04320 11111111111111111111111111111111
+*L04352 11111111111101110111111110111111
+*L04384 11111111101111111111101111111111
+*L04416 11111111111111110111111110111111
+*L04448 10111111111111111111111111110111
+*L04480 11111110111111111111111101111111
+*L04512 11111111111110111111111110111111
+*L04544 11111111111111111110111111111111
+*L04576 11111111111111111111111111111110
+*L04608 11111011111100000000000000000000
+*L04864 00000000000000000000111111111111
+*L04896 11111111111111111111111111111111
+*L04928 11110111101110111011111110111111
+*L04960 11110111111111111111111111111111
+*L04992 11110111111111101111111111111011
+*L05024 11111111111111111111111111101111
+*L05056 11111111111111111111011111111111
+*L05088 11111110111111111111111111111111
+*L05120 11111111111111111110011111111111
+*L05152 11111011111111111111111111111110
+*L05184 11111111111111111111101111111111
+*L05216 11111111111011111111000000000000
+*L05344 00000000000000000000000011111111
+*L05376 11111111111111111111111111111111
+*L05408 11111111101111111111011111111111
+*L05440 11101111111111111111011111111111
+*L05472 11111111111111111110111111111111
+*L05504 11111111111111111111111111011110
+*L05536 11111111000000000000000000000000
+*L05792 00000000000000000101110000001000
+*L05824 10110011000000110100001000000000
+*C06AA
+*CBD4 \ No newline at end of file
diff --git a/v1.2/pld/abc80-1m-ic4.mx b/v1.2/pld/abc80-1m-ic4.mx
new file mode 100644
index 0000000..b6d82ea
--- /dev/null
+++ b/v1.2/pld/abc80-1m-ic4.mx
@@ -0,0 +1,106 @@
+Name abc80-1m-ic4 ;
+PartNo 04 ;
+Date 2021-01-24 ;
+Revision 1.2.0 ;
+Designer H. Peter Anvin ;
+Company Self ;
+Assembly abc80-1m-sram ;
+Location IC4 ;
+Device g22v10 ;
+
+/* *************** INPUT PINS *********************/
+PIN 1 = CLK;
+PIN 2 = MREQn;
+PIN 3 = A1;
+PIN 4 = A0;
+PIN 5 = A4;
+PIN 6 = WRn;
+PIN 7 = RDn;
+PIN 8 = ROMMAPn;
+PIN 9 = BYPASSn; /* IORQ# RFSH# or boot mode */
+PIN 10 = IOSELn; /* IORQ# !M1# A2=1 */
+PIN 11 = MD7;
+PIN 13 = MD6;
+
+/* *************** OUTPUT PINS *********************/
+PIN 14 = MA4;
+PIN 15 = TKN80EN;
+PIN 16 = !BUFEN;
+PIN 17 = MAPWR;
+PIN 18 = !CS0;
+PIN 19 = !CS1;
+PIN 20 = !CS2;
+PIN 21 = OEn;
+PIN 22 = !WE;
+PIN 23 = !MREQ_SYS;
+
+false = 'b'0;
+true = 'b'1;
+
+/* Memory access directed to system */
+system = !BYPASSn # (MD7 & MD6);
+ourmem = !MREQn & !system;
+
+/* Addressing the map memory */
+mapio = !IOSELn & A4;
+/* Addressing the control register */
+ctlio = !IOSELn & !WRn & A1 & A0;
+
+/* Traces the external signal MUXA */
+muxa = !MREQn & BUFEN;
+
+MREQ_SYS = !MREQn & system & !BUFEN;
+
+WE = BUFEN & !WRn & (!MREQn # (!IOSELn & A4));
+OEn = BUFEN & !(!RDn & (!MREQn # (!IOSELn & A4)));
+
+/* Enable the input/output buffer, and the B mux */
+BUFEN.ar = false;
+BUFEN.d = ((!MREQn # !IOSELn) & BUFEN) #
+ (!BUFEN & (ourmem # mapio # ctlio));
+
+/*
+ * TKN80 handling. Note that RD# = 0 MREQ# = 1 is only possible for a
+ * true I/O access (IORQ# = 0, M1# = 1). IOSEL# = 0 means A2 = 1 and
+ * vice versa.
+ */
+TKN80EN.ar = false;
+TKN80EN.d = (MREQn & !RDn & IOSELn & !A4 & !A1 & !A0) #
+ (TKN80EN & !(MREQn & !RDn & !IOSELn & !A4 & A1 & A0));
+
+/*
+ * MA4: TKN80EN when accessing maps, A4 pass through when accessing memory
+ */
+MA4 = (!muxa & TKN80EN) # (muxa & A4);
+
+/*
+ * MAPWR is a clock signal; drive it high one cycle into the
+ * writing of the control register, similar to the assertion of CS#
+ * (see below.)
+ */
+MAPWR.ar = false;
+MAPWR.d = ctlio & BUFEN;
+
+/*
+ * For the chip selects, assert the one appropriate for the map when
+ * neither MREQ# nor IOSEL# is asserted. Assert the new one on the first
+ * clock cycle together with BUFEN, and MUXA for a memory reference.
+ *
+ * For an I/O write cycle, delay CS# by one cycle since WR# is asserted
+ * immediately, unlike for a memory cycle. This is done by simply
+ * looking to see if BUFEN is already asserted.
+ */
+CS0.ar = false;
+CS0.d = (MREQn & IOSELn & ROMMAPn) #
+ (!BUFEN & !MREQn & BYPASSn & !MD7 & !MD6) #
+ (BUFEN & !MREQn & CS0) #
+ (mapio & ((!A1 & !A0) # (A1 & A0)) & (!RDn # (!WRn & BUFEN)));
+CS1.ar = false;
+CS1.d = (!BUFEN & !MREQn & BYPASSn & !MD7 & MD6) #
+ (BUFEN & !MREQn & CS1) #
+ (mapio & !A1 & A0 & (!RDn # (!WRn & BUFEN)));
+CS2.ar = false;
+CS2.d = (MREQn & IOSELn & !ROMMAPn) #
+ (!BUFEN & !MREQn & BYPASSn & MD7 & !MD6) #
+ (BUFEN & !MREQn & CS2) #
+ (mapio & A1 & !A0 & (!RDn # (!WRn & BUFEN)));
diff --git a/v1.2/pld/abc80-1m-ic4.pdf b/v1.2/pld/abc80-1m-ic4.pdf
new file mode 100644
index 0000000..d234a42
--- /dev/null
+++ b/v1.2/pld/abc80-1m-ic4.pdf
@@ -0,0 +1,225 @@
+{COMPONENT Z:\HOME\HPA\ABC80\1M\V1.2\PLD\ABC80-1M-IC4.SYM
+
+ {ENVIRONMENT
+ {PDIFvrev 3.00}
+ {Program "CUPL(WM) Version 5.0a"}
+ {DBtype "Schematic"}
+ {DBvrev 1.01}
+ {DBtime "Sun Jan 24 16:30:45 2021 "}
+ {DBunit "MIL"}
+ {DBgrid 10}
+ {Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1
+ "PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1
+ "DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4
+ "CMPNAM" 5 "BORDER" 5}
+ }
+
+ {USER
+ {VIEW
+ {Mode SYMB}
+ {Nlst OPEN}
+ {Vw 0 0 2}
+ {Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
+ {Gs 10 10}
+ }
+ }
+
+ {DISPLAY
+ [Ly "PINNUM"]
+ [Ls "SOLID"][Wd 0]
+ [Ts 15][Tj "LC"][Tr 0][Tm "N"]
+ }
+
+ {SYMBOL
+ {PIN_DEF
+ [Ly "PINCON"]
+ {P CLK {Pt "INPUT"}{Lq 0}{Ploc 100 260}}
+ {P MREQN {Pt "INPUT"}{Lq 0}{Ploc 100 220}}
+ {P A1 {Pt "INPUT"}{Lq 0}{Ploc 100 200}}
+ {P A0 {Pt "INPUT"}{Lq 0}{Ploc 100 180}}
+ {P A4 {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
+ {P WRN {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
+ {P RDN {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
+ {P ROMMAPN {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
+ {P BYPASSN {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
+ {P IOSELN {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
+ {P MD7 {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
+ {P MD6 {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
+ {P MA4 {Pt "I/O"}{Lq 0}{Ploc 350 20}}
+ {P OEN {Pt "I/O"}{Lq 0}{Ploc 350 40}}
+ {P WE' {Pt "I/O"}{Lq 0}{Ploc 350 60}}
+ {P MREQ_SYS' {Pt "I/O"}{Lq 0}{Ploc 350 80}}
+ {P TKN80EN {Pt "OUTPUT"}{Lq 0}{Ploc 350 100}}
+ {P BUFEN' {Pt "OUTPUT"}{Lq 0}{Ploc 350 120}}
+ {P MAPWR {Pt "OUTPUT"}{Lq 0}{Ploc 350 140}}
+ {P CS0' {Pt "OUTPUT"}{Lq 0}{Ploc 350 160}}
+ {P CS1' {Pt "OUTPUT"}{Lq 0}{Ploc 350 180}}
+ {P CS2' {Pt "OUTPUT"}{Lq 0}{Ploc 350 200}}
+ }
+
+ {PKG
+ [Ly "REFDES"]
+ [Ts 25][Tj "CB"][Tr 0][Tm "N"]
+ {Rdl 225 290}
+
+ [Ly "PINNUM"]
+ [Ts 15][Tj "RC"]
+ {Pnl 120 270}
+ [Ts 15][Tj "RC"]
+ {Pnl 120 230}
+ {Pnl 120 210}
+ {Pnl 120 190}
+ {Pnl 120 170}
+ {Pnl 120 150}
+ {Pnl 120 130}
+ {Pnl 120 110}
+ {Pnl 120 90}
+ {Pnl 120 70}
+ {Pnl 120 50}
+ {Pnl 120 30}
+ [Ts 15][Tj "LC"]
+ {Pnl 330 30}
+ {Pnl 330 50}
+ {Pnl 330 70}
+ {Pnl 330 90}
+ {Pnl 330 110}
+ {Pnl 330 130}
+ {Pnl 330 150}
+ {Pnl 330 170}
+ {Pnl 330 190}
+ {Pnl 330 210}
+
+ {Sd A 1 2 3 4 5 6 7 8 9 10 11 13 14 21 22 23 15 16 17 18 19 20}
+ }
+
+ {PIC
+ [Ly "GATE"]
+ [Ts 15][Tj "LC"][Tr 0][Tm "N"]
+ {R 130 280 320 0}
+ {L 130 260 100 260}
+ {L 130 270 140 260 130 250}
+ {L 130 220 100 220}
+ {L 130 200 100 200}
+ {L 130 180 100 180}
+ {L 130 160 100 160}
+ {L 130 140 100 140}
+ {L 130 120 100 120}
+ {L 130 100 100 100}
+ {L 130 80 100 80}
+ {L 130 60 100 60}
+ {L 130 40 100 40}
+ {L 130 20 100 20}
+ {L 320 20 350 20}
+ {L 320 40 350 40}
+ {C 325 60 5}
+ {L 330 60 350 60}
+ {C 325 80 5}
+ {L 330 80 350 80}
+ {L 320 100 350 100}
+ {C 325 120 5}
+ {L 330 120 350 120}
+ {L 320 140 350 140}
+ {C 325 160 5}
+ {L 330 160 350 160}
+ {C 325 180 5}
+ {L 330 180 350 180}
+ {C 325 200 5}
+ {L 330 200 350 200}
+ [Ly "PINNAM"]
+ [Tj "LC"]
+ {T "CLK" 140 260}
+ {T "MREQN" 140 220}
+ {T "A1" 140 200}
+ {T "A0" 140 180}
+ {T "A4" 140 160}
+ {T "WRN" 140 140}
+ {T "RDN" 140 120}
+ {T "ROMMAPN" 140 100}
+ {T "BYPASSN" 140 80}
+ {T "IOSELN" 140 60}
+ {T "MD7" 140 40}
+ {T "MD6" 140 20}
+ [Tj "RC"]
+ {T "MA4" 310 20}
+ {T "OEN" 310 40}
+ {T "WE'" 310 60}
+ {T "MREQ_SYS'" 310 80}
+ {T "TKN80EN" 310 100}
+ {T "BUFEN'" 310 120}
+ {T "MAPWR" 310 140}
+ {T "CS0'" 310 160}
+ {T "CS1'" 310 180}
+ {T "CS2'" 310 200}
+ [Ly "DEVICE"]
+ [Tj "CT"]
+ {T "G22V10" 225 -10}
+ }
+
+ {ATR
+ {IN
+ {Org 100 20}
+ {Ty 255}
+ }
+ {EX
+ [Ly "ATTR2"]
+ [Ts 12][Tj "CT"][Tr 0][Tm "N"]
+ {At PLD Z:\HOME\HPA\ABC80\1M\V1.2\PLD\ABC80-1M-IC4 225 280}
+ }
+ }
+ }
+
+ {DETAIL
+ {ANNOTATE
+ }
+
+ {NET_DEF
+ {N CLK
+ }
+ {N MREQN
+ }
+ {N A1
+ }
+ {N A0
+ }
+ {N A4
+ }
+ {N WRN
+ }
+ {N RDN
+ }
+ {N ROMMAPN
+ }
+ {N BYPASSN
+ }
+ {N IOSELN
+ }
+ {N MD7
+ }
+ {N MD6
+ }
+ {N MA4
+ }
+ {N OEN
+ }
+ {N WE'
+ }
+ {N MREQ_SYS'
+ }
+ {N TKN80EN
+ }
+ {N BUFEN'
+ }
+ {N MAPWR
+ }
+ {N CS0'
+ }
+ {N CS1'
+ }
+ {N CS2'
+ }
+ }
+
+ {SUBCOMP
+ }
+ }
+}
diff --git a/v1.2/pld/abc80-1m-ic4.pla b/v1.2/pld/abc80-1m-ic4.pla
new file mode 100644
index 0000000..d991cb3
--- /dev/null
+++ b/v1.2/pld/abc80-1m-ic4.pla
@@ -0,0 +1,82 @@
+# Berkeley PLA format generated using
+#
+# CUPL(WM) 5.0a Serial# 60008009
+# Device g22v10 Library DLIB-h-40-1
+# Created Sun Jan 24 16:30:45 2021
+# Name abc80-1m-ic4
+# Partno 04
+# Revision 1.2.0
+# Date 2021-01-24
+# Designer H. Peter Anvin
+# Company Self
+# Assembly abc80-1m-sram
+# Location IC4
+#
+# Inputs 0 1 A0 A1
+# A4 !BUFEN BYPASSn CLK
+# !CS0 !CS1 !CS2 IOSELn
+# MA4 MAPWR MD6 MD7
+# !MREQ_SYS MREQn OEn RDn
+# ROMMAPn TKN80EN !WE WRn
+# Outputs !BUFEN.d BUFEN.ar !CS0.d CS0.ar
+# !CS1.d CS1.ar !CS2.d CS2.ar
+# MA4 MAPWR.d MAPWR.ar !MREQ_SYS
+# OEn TKN80EN.d TKN80EN.ar !WE
+# BUFEN.oe CS0.oe CS1.oe CS2.oe
+# MA4.oe MAPWR.oe MREQ_SYS.oe OEn.oe
+# TKN80EN.oe WE.oe
+.i 24
+.o 26
+.p 51
+--11-------0-----------0 1~~~~~~~~~~~~~~~~~~~~~~~~~
+------1--------0-0------ 1~~~~~~~~~~~~~~~~~~~~~~~~~
+------1-------0--0------ 1~~~~~~~~~~~~~~~~~~~~~~~~~
+----1------0------------ 1~~~~~~~~~~~~~~~~~~~~~~~~~
+-----1-----------0------ 1~~~~~~~~~~~~~~~~~~~~~~~~~
+-----1-----0------------ 1~~~~~~~~~~~~~~~~~~~~~~~~~
+1----------------------- ~1~1~1~1~~1~~~1~~~~~~~~~~~
+-----01-------00-0------ ~~1~~~~~~~~~~~~~~~~~~~~~~~
+--0011-----0-----------0 ~~1~~~~~~~~~~~~~~~~~~~~~~~
+--1111-----0-----------0 ~~1~~~~~~~~~~~~~~~~~~~~~~~
+--001------0-------0---- ~~1~~~~~~~~~~~~~~~~~~~~~~~
+--111------0-------0---- ~~1~~~~~~~~~~~~~~~~~~~~~~~
+-----------1-----1--1--- ~~1~~~~~~~~~~~~~~~~~~~~~~~
+-----1--1--------0------ ~~1~~~~~~~~~~~~~~~~~~~~~~~
+-----01-------10-0------ ~~~~1~~~~~~~~~~~~~~~~~~~~~
+--1011-----0-----------0 ~~~~1~~~~~~~~~~~~~~~~~~~~~
+--101------0-------0---- ~~~~1~~~~~~~~~~~~~~~~~~~~~
+-----1---1-------0------ ~~~~1~~~~~~~~~~~~~~~~~~~~~
+--0111-----0-----------0 ~~~~~~1~~~~~~~~~~~~~~~~~~~
+-----01-------01-0------ ~~~~~~1~~~~~~~~~~~~~~~~~~~
+--011------0-------0---- ~~~~~~1~~~~~~~~~~~~~~~~~~~
+-----------1-----1--0--- ~~~~~~1~~~~~~~~~~~~~~~~~~~
+-----1----1------0------ ~~~~~~1~~~~~~~~~~~~~~~~~~~
+----11-----------0------ ~~~~~~~~1~~~~~~~~~~~~~~~~~
+-----------------1---1-- ~~~~~~~~1~~~~~~~~~~~~~~~~~
+-----0---------------1-- ~~~~~~~~1~~~~~~~~~~~~~~~~~
+--11-1-----0-----------0 ~~~~~~~~~1~~~~~~~~~~~~~~~~
+-----0--------11-0------ ~~~~~~~~~~~1~~~~~~~~~~~~~~
+-----00----------0------ ~~~~~~~~~~~1~~~~~~~~~~~~~~
+-----1-----1-----1------ ~~~~~~~~~~~~1~~~~~~~~~~~~~
+----01-----------1------ ~~~~~~~~~~~~1~~~~~~~~~~~~~
+-----1-------------1---- ~~~~~~~~~~~~1~~~~~~~~~~~~~
+--000------1-----1-0---- ~~~~~~~~~~~~~1~~~~~~~~~~~~
+-------------------1-1-- ~~~~~~~~~~~~~1~~~~~~~~~~~~
+-----------------0---1-- ~~~~~~~~~~~~~1~~~~~~~~~~~~
+----1----------------1-- ~~~~~~~~~~~~~1~~~~~~~~~~~~
+-----------1---------1-- ~~~~~~~~~~~~~1~~~~~~~~~~~~
+---0-----------------1-- ~~~~~~~~~~~~~1~~~~~~~~~~~~
+--0------------------1-- ~~~~~~~~~~~~~1~~~~~~~~~~~~
+----11-----0-----------0 ~~~~~~~~~~~~~~~1~~~~~~~~~~
+-----1-----------0-----0 ~~~~~~~~~~~~~~~1~~~~~~~~~~
+-1---------------------- ~~~~~~~~~~~~~~~~1~~~~~~~~~
+-1---------------------- ~~~~~~~~~~~~~~~~~1~~~~~~~~
+-1---------------------- ~~~~~~~~~~~~~~~~~~1~~~~~~~
+-1---------------------- ~~~~~~~~~~~~~~~~~~~1~~~~~~
+-1---------------------- ~~~~~~~~~~~~~~~~~~~~1~~~~~
+-1---------------------- ~~~~~~~~~~~~~~~~~~~~~1~~~~
+-1---------------------- ~~~~~~~~~~~~~~~~~~~~~~1~~~
+-1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~1~~
+-1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~1~
+-1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~1
+.end
diff --git a/v1.2/pld/abc80-1m-ic4.pld b/v1.2/pld/abc80-1m-ic4.pld
new file mode 100644
index 0000000..b6d82ea
--- /dev/null
+++ b/v1.2/pld/abc80-1m-ic4.pld
@@ -0,0 +1,106 @@
+Name abc80-1m-ic4 ;
+PartNo 04 ;
+Date 2021-01-24 ;
+Revision 1.2.0 ;
+Designer H. Peter Anvin ;
+Company Self ;
+Assembly abc80-1m-sram ;
+Location IC4 ;
+Device g22v10 ;
+
+/* *************** INPUT PINS *********************/
+PIN 1 = CLK;
+PIN 2 = MREQn;
+PIN 3 = A1;
+PIN 4 = A0;
+PIN 5 = A4;
+PIN 6 = WRn;
+PIN 7 = RDn;
+PIN 8 = ROMMAPn;
+PIN 9 = BYPASSn; /* IORQ# RFSH# or boot mode */
+PIN 10 = IOSELn; /* IORQ# !M1# A2=1 */
+PIN 11 = MD7;
+PIN 13 = MD6;
+
+/* *************** OUTPUT PINS *********************/
+PIN 14 = MA4;
+PIN 15 = TKN80EN;
+PIN 16 = !BUFEN;
+PIN 17 = MAPWR;
+PIN 18 = !CS0;
+PIN 19 = !CS1;
+PIN 20 = !CS2;
+PIN 21 = OEn;
+PIN 22 = !WE;
+PIN 23 = !MREQ_SYS;
+
+false = 'b'0;
+true = 'b'1;
+
+/* Memory access directed to system */
+system = !BYPASSn # (MD7 & MD6);
+ourmem = !MREQn & !system;
+
+/* Addressing the map memory */
+mapio = !IOSELn & A4;
+/* Addressing the control register */
+ctlio = !IOSELn & !WRn & A1 & A0;
+
+/* Traces the external signal MUXA */
+muxa = !MREQn & BUFEN;
+
+MREQ_SYS = !MREQn & system & !BUFEN;
+
+WE = BUFEN & !WRn & (!MREQn # (!IOSELn & A4));
+OEn = BUFEN & !(!RDn & (!MREQn # (!IOSELn & A4)));
+
+/* Enable the input/output buffer, and the B mux */
+BUFEN.ar = false;
+BUFEN.d = ((!MREQn # !IOSELn) & BUFEN) #
+ (!BUFEN & (ourmem # mapio # ctlio));
+
+/*
+ * TKN80 handling. Note that RD# = 0 MREQ# = 1 is only possible for a
+ * true I/O access (IORQ# = 0, M1# = 1). IOSEL# = 0 means A2 = 1 and
+ * vice versa.
+ */
+TKN80EN.ar = false;
+TKN80EN.d = (MREQn & !RDn & IOSELn & !A4 & !A1 & !A0) #
+ (TKN80EN & !(MREQn & !RDn & !IOSELn & !A4 & A1 & A0));
+
+/*
+ * MA4: TKN80EN when accessing maps, A4 pass through when accessing memory
+ */
+MA4 = (!muxa & TKN80EN) # (muxa & A4);
+
+/*
+ * MAPWR is a clock signal; drive it high one cycle into the
+ * writing of the control register, similar to the assertion of CS#
+ * (see below.)
+ */
+MAPWR.ar = false;
+MAPWR.d = ctlio & BUFEN;
+
+/*
+ * For the chip selects, assert the one appropriate for the map when
+ * neither MREQ# nor IOSEL# is asserted. Assert the new one on the first
+ * clock cycle together with BUFEN, and MUXA for a memory reference.
+ *
+ * For an I/O write cycle, delay CS# by one cycle since WR# is asserted
+ * immediately, unlike for a memory cycle. This is done by simply
+ * looking to see if BUFEN is already asserted.
+ */
+CS0.ar = false;
+CS0.d = (MREQn & IOSELn & ROMMAPn) #
+ (!BUFEN & !MREQn & BYPASSn & !MD7 & !MD6) #
+ (BUFEN & !MREQn & CS0) #
+ (mapio & ((!A1 & !A0) # (A1 & A0)) & (!RDn # (!WRn & BUFEN)));
+CS1.ar = false;
+CS1.d = (!BUFEN & !MREQn & BYPASSn & !MD7 & MD6) #
+ (BUFEN & !MREQn & CS1) #
+ (mapio & !A1 & A0 & (!RDn # (!WRn & BUFEN)));
+CS2.ar = false;
+CS2.d = (MREQn & IOSELn & !ROMMAPn) #
+ (!BUFEN & !MREQn & BYPASSn & MD7 & !MD6) #
+ (BUFEN & !MREQn & CS2) #
+ (mapio & A1 & !A0 & (!RDn # (!WRn & BUFEN)));
diff --git a/v1.2/pld/abc80-1m-ic4.sim b/v1.2/pld/abc80-1m-ic4.sim
new file mode 100644
index 0000000..258cacd
--- /dev/null
+++ b/v1.2/pld/abc80-1m-ic4.sim
@@ -0,0 +1,156 @@
+%SIGNAL
+PIN 4 = A0
+PIN 3 = A1
+PIN 5 = A4
+PIN 16 = !BUFEN
+PIN 9 = BYPASSn
+PIN 1 = CLK
+PIN 18 = !CS0
+PIN 19 = !CS1
+PIN 20 = !CS2
+PIN 10 = IOSELn
+PIN 14 = MA4
+PIN 17 = MAPWR
+PIN 13 = MD6
+PIN 11 = MD7
+PIN 23 = !MREQ_SYS
+PIN 2 = MREQn
+PIN 21 = OEn
+PIN 7 = RDn
+PIN 8 = ROMMAPn
+PIN 15 = TKN80EN
+PIN 22 = !WE
+PIN 6 = WRn
+%END
+
+%FIELD
+%END
+
+%EQUATION
+BUFEN.d =>
+ A0 & A1 & !IOSELn & !WRn
+ # BYPASSn & !MD7 & !MREQn
+ # BYPASSn & !MD6 & !MREQn
+ # A4 & !IOSELn
+ # !BUFEN & !MREQn
+ # !BUFEN & !IOSELn
+
+BUFEN.ar CS0.ar CS1.ar CS2.ar MAPWR.ar TKN80EN.ar =>
+ 0
+
+CS0.d =>
+ BUFEN & BYPASSn & !MD6 & !MD7 & !MREQn
+ # !A0 & !A1 & A4 & !BUFEN & !IOSELn & !WRn
+ # A0 & A1 & A4 & !BUFEN & !IOSELn & !WRn
+ # !A0 & !A1 & A4 & !IOSELn & !RDn
+ # A0 & A1 & A4 & !IOSELn & !RDn
+ # IOSELn & MREQn & ROMMAPn
+ # !BUFEN & !CS0 & !MREQn
+
+CS0.ar =>
+
+CS1.d =>
+ BUFEN & BYPASSn & MD6 & !MD7 & !MREQn
+ # A0 & !A1 & A4 & !BUFEN & !IOSELn & !WRn
+ # A0 & !A1 & A4 & !IOSELn & !RDn
+ # !BUFEN & !CS1 & !MREQn
+
+CS1.ar =>
+
+CS2.d =>
+ !A0 & A1 & A4 & !BUFEN & !IOSELn & !WRn
+ # BUFEN & BYPASSn & !MD6 & MD7 & !MREQn
+ # !A0 & A1 & A4 & !IOSELn & !RDn
+ # IOSELn & MREQn & !ROMMAPn
+ # !BUFEN & !CS2 & !MREQn
+
+CS2.ar =>
+
+MA4 =>
+ A4 & !BUFEN & !MREQn
+ # MREQn & !TKN80EN
+ # BUFEN & !TKN80EN
+
+MAPWR.d =>
+ A0 & A1 & !BUFEN & !IOSELn & !WRn
+
+MAPWR.ar =>
+
+MREQ_SYS =>
+ BUFEN & MD6 & MD7 & !MREQn
+ # BUFEN & !BYPASSn & !MREQn
+
+OEn =>
+ !BUFEN & IOSELn & MREQn
+ # !A4 & !BUFEN & MREQn
+ # !BUFEN & RDn
+
+TKN80EN.d =>
+ !A0 & !A1 & !A4 & IOSELn & MREQn & !RDn
+ # RDn & !TKN80EN
+ # !MREQn & !TKN80EN
+ # A4 & !TKN80EN
+ # IOSELn & !TKN80EN
+ # !A1 & !TKN80EN
+ # !A0 & !TKN80EN
+
+TKN80EN.ar =>
+
+WE =>
+ A4 & !BUFEN & !IOSELn & !WRn
+ # !BUFEN & !MREQn & !WRn
+
+ctlio =>
+ A0 & A1 & !IOSELn & !WRn
+
+false =>
+ 0
+
+mapio =>
+ A4 & !IOSELn
+
+muxa =>
+ BUFEN & !MREQn
+
+ourmem =>
+ BYPASSn & !MD6 & !MREQn
+ # BYPASSn & !MD7 & !MREQn
+
+system =>
+ !BYPASSn
+ # MD6 & MD7
+
+true =>
+ 1
+
+BUFEN.oe =>
+ 1
+
+CS0.oe =>
+ 1
+
+CS1.oe =>
+ 1
+
+CS2.oe =>
+ 1
+
+MA4.oe =>
+ 1
+
+MAPWR.oe =>
+ 1
+
+MREQ_SYS.oe =>
+ 1
+
+OEn.oe =>
+ 1
+
+TKN80EN.oe =>
+ 1
+
+WE.oe =>
+ 1
+
+%END
diff --git a/v1.2/pld/abc80-1m-ic5.abs b/v1.2/pld/abc80-1m-ic5.abs
new file mode 100644
index 0000000..b7e1baf
--- /dev/null
+++ b/v1.2/pld/abc80-1m-ic5.abs
Binary files differ
diff --git a/v1.2/pld/abc80-1m-ic5.doc b/v1.2/pld/abc80-1m-ic5.doc
new file mode 100644
index 0000000..f51f910
--- /dev/null
+++ b/v1.2/pld/abc80-1m-ic5.doc
@@ -0,0 +1,331 @@
+
+*******************************************************************************
+ abc80-1m-ic5
+*******************************************************************************
+
+CUPL(WM) 5.0a Serial# 60008009
+Device g22v10 Library DLIB-h-40-1
+Created Sun Sep 06 14:23:02 2020
+Name abc80-1m-ic5
+Partno 05
+Revision 1.1.2
+Date 2020-09-05
+Designer H. Peter Anvin
+Company Self
+Assembly abc80-1m-sram
+Location IC5
+
+===============================================================================
+ Expanded Product Terms
+===============================================================================
+
+BYPASSn =>
+ BOOTn & IORQn & RESETn & RFSHn
+
+INT.d =>
+ INT & !MD6 & !MD7
+ # MD6 & MD7
+
+INT.ar =>
+ !RESETn
+
+INT.oe =>
+ INT & !IRQDIS
+
+IORQ_SYSn =>
+ A2 & A4 & M1n
+ # IORQn
+
+IOSEL =>
+ A2 & !IORQn & M1n
+
+IRQDIS =>
+ IRQDIS & !MD7 & NMI_SYSn & RESETn
+ # IRQDIS & !MAPWR & NMI_SYSn & RESETn
+ # !INT & IRQDIS & !MD7 & RESETn
+ # !INT & IRQDIS & !MAPWR & RESETn
+ # MAPWR & MD6
+
+MA3 =>
+ A3 & !BUFENn
+
+NMI =>
+ !INT & !IRQDIS & !NMI_SYSn
+
+ROMMAPn.d =>
+ !MD4
+
+ROMMAPn.ar =>
+ !RESETn
+
+false =>
+ 0
+
+inten =>
+ INT
+
+nmien =>
+ !INT & !IRQDIS
+
+true =>
+ 1
+
+A4.oe =>
+ 0
+
+BYPASSn.oe =>
+ 1
+
+IORQ_SYSn.oe =>
+ 1
+
+IOSEL.oe =>
+ 1
+
+IRQDIS.oe =>
+ 1
+
+MA3.oe =>
+ 1
+
+NMI.oe =>
+ 1
+
+NMI_SYSn.oe =>
+ 0
+
+ROMMAPn.oe =>
+ 1
+
+
+===============================================================================
+ Symbol Table
+===============================================================================
+
+Pin Variable Pterms Max Min
+Pol Name Ext Pin Type Used Pterms Level
+--- -------- --- --- ---- ------ ------ -----
+
+ A2 6 V - - -
+ A3 4 V - - -
+ A4 14 V - - -
+ BOOTn 3 V - - -
+ BUFENn 10 V - - -
+ BYPASSn 16 V 1 12 4
+ ! INT 20 V - - -
+ ! INT d 20 X 2 14 4
+ INT ar 20 X 1 1 1
+ INT oe 20 X 1 1 1
+ IORQ_SYSn 23 V 2 8 4
+ IORQn 2 V - - -
+ ! IOSEL 15 V 1 10 4
+ IRQDIS 19 V 5 16 4
+ M1n 7 V - - -
+ MA3 18 V 1 16 4
+ MAPWR 1 V - - -
+ MD4 11 V - - -
+ MD6 9 V - - -
+ MD7 13 V - - -
+ ! NMI 22 V 1 10 4
+ NMI_SYSn 21 V - - -
+ RESETn 5 V - - -
+ RFSHn 8 V - - -
+ ROMMAPn 17 V - - -
+ ROMMAPn d 17 X 1 14 4
+ ROMMAPn ar 17 X 1 1 1
+ false 0 I 1 - -
+ inten 0 I 1 - -
+ nmien 0 I 1 - -
+ true 0 I 1 - -
+ A4 oe 14 D 1 1 0
+ BYPASSn oe 16 D 1 1 0
+ IORQ_SYSn oe 23 D 1 1 0
+ IOSEL oe 15 D 1 1 0
+ IRQDIS oe 19 D 1 1 0
+ MA3 oe 18 D 1 1 0
+ NMI oe 22 D 1 1 0
+ NMI_SYSn oe 21 D 1 1 0
+ ROMMAPn oe 17 D 1 1 0
+
+
+LEGEND D : default variable F : field G : group
+ I : intermediate variable N : node M : extended node
+ U : undefined V : variable X : extended variable
+ T : function
+
+
+===============================================================================
+ Fuse Plot
+===============================================================================
+
+SP
+ 05764 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+
+AR
+ 00000 -----------------x--------------------------
+
+Pin #23 05808 Mode --
+ 00044 --------------------------------------------
+ 00088 --------------------x---x-------------x-----
+ 00132 ----x---------------------------------------
+ 00176 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00220 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00264 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00308 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00352 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00396 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #22 05810 Mode x-
+ 00440 --------------------------------------------
+ 00484 -----------x--x----x------------------------
+ 00528 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00572 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00616 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00660 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00704 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00748 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00792 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00836 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00880 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #21 05812 Mode x-
+ 00924 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 00968 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01012 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01056 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01100 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01144 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01188 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01232 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01276 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01320 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01364 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01408 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01452 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #20 05814 Mode xx
+ 01496 ---------------x---x------------------------
+ 01540 ---------------x-----------------x---------x
+ 01584 --------------------------------x---------x-
+ 01628 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01672 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01716 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01760 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01804 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01848 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01892 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01936 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 01980 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02024 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02068 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02112 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #19 05816 Mode --
+ 02156 --------------------------------------------
+ 02200 ----------x-----x-x------------------------x
+ 02244 -x--------x-----x-x-------------------------
+ 02288 --------------x-x-x------------------------x
+ 02332 -x------------x-x-x-------------------------
+ 02376 x-------------------------------x-----------
+ 02420 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02464 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02508 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02552 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02596 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02640 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02684 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02728 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02772 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02816 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 02860 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #18 05818 Mode --
+ 02904 --------------------------------------------
+ 02948 ------------x------------------------x------
+ 02992 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03036 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03080 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03124 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03168 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03212 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03256 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03300 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03344 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03388 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03432 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03476 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03520 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03564 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03608 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #17 05820 Mode -x
+ 03652 --------------------------------------------
+ 03696 -----------------------------------------x--
+ 03740 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03784 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03828 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03872 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03916 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 03960 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04004 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04048 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04092 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04136 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04180 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04224 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04268 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #16 05822 Mode --
+ 04312 --------------------------------------------
+ 04356 ----x---x-------x-----------x---------------
+ 04400 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04444 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04488 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04532 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04576 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04620 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04664 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04708 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04752 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04796 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 04840 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #15 05824 Mode x-
+ 04884 --------------------------------------------
+ 04928 -----x--------------x---x-------------------
+ 04972 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05016 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05060 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05104 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05148 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05192 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05236 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05280 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05324 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+Pin #14 05826 Mode x-
+ 05368 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05412 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05456 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05500 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05544 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05588 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05632 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05676 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+ 05720 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
+
+
+LEGEND X : fuse not blown
+ - : fuse blown
+
+===============================================================================
+ Chip Diagram
+===============================================================================
+
+ ______________
+ | abc80-1m-ic5 |
+ MAPWR x---|1 24|---x Vcc
+ IORQn x---|2 23|---x IORQ_SYSn
+ BOOTn x---|3 22|---x !NMI
+ A3 x---|4 21|---x NMI_SYSn
+ RESETn x---|5 20|---x !INT
+ A2 x---|6 19|---x IRQDIS
+ M1n x---|7 18|---x MA3
+ RFSHn x---|8 17|---x ROMMAPn
+ MD6 x---|9 16|---x BYPASSn
+ BUFENn x---|10 15|---x !IOSEL
+ MD4 x---|11 14|---x A4
+ GND x---|12 13|---x MD7
+ |______________|
+
diff --git a/v1.2/pld/abc80-1m-ic5.jed b/v1.2/pld/abc80-1m-ic5.jed
new file mode 100644
index 0000000..6d12540
--- /dev/null
+++ b/v1.2/pld/abc80-1m-ic5.jed
@@ -0,0 +1,59 @@
+
+CUPL(WM) 5.0a Serial# 60008009
+Device g22v10 Library DLIB-h-40-1
+Created Sun Sep 06 14:23:02 2020
+Name abc80-1m-ic5
+Partno 05
+Revision 1.1.2
+Date 2020-09-05
+Designer H. Peter Anvin
+Company Self
+Assembly abc80-1m-sram
+Location IC5
+*QP24
+*QF5892
+*G0
+*F0
+*L00000 11111111111111111011111111111111
+*L00032 11111111111111111111111111111111
+*L00064 11111111111111111111111111111111
+*L00096 11111111111101110111111111111101
+*L00128 11111111011111111111111111111111
+*L00160 11111111111111110000000000000000
+*L00416 00000000000000000000000011111111
+*L00448 11111111111111111111111111111111
+*L00480 11111111111111101101111011111111
+*L00512 11111111111111110000000000000000
+*L01472 00000000000000000000000011111111
+*L01504 11111110111011111111111111111111
+*L01536 11111111111111111110111111111111
+*L01568 11111011111111101111111111111111
+*L01600 11111111111111110111111111010000
+*L02144 00000000000011111111111111111111
+*L02176 11111111111111111111111111111111
+*L02208 11011111010111111111111111111111
+*L02240 11101011111111011111010111111111
+*L02272 11111111111111111111111111111101
+*L02304 01011111111111111111111111101011
+*L02336 11111111110101011111111111111111
+*L02368 11111111011111111111111111111111
+*L02400 11111111011111111111000000000000
+*L02880 00000000000000000000000011111111
+*L02912 11111111111111111111111111111111
+*L02944 11111111111111110111111111111111
+*L02976 11111111101111110000000000000000
+*L03648 00001111111111111111111111111111
+*L03680 11111111111111111111111111111111
+*L03712 11111111111111111111111110110000
+*L04288 00000000000000000000000011111111
+*L04320 11111111111111111111111111111111
+*L04352 11111111011101111111011111111111
+*L04384 01111111111111110000000000000000
+*L04864 00000000000000000000111111111111
+*L04896 11111111111111111111111111111111
+*L04928 11111011111111111111011101111111
+*L04960 11111111111100000000000000000000
+*L05792 00000000000000001101010011111011
+*L05824 01010011000000110101001000000000
+*C7C06
+*949E \ No newline at end of file
diff --git a/v1.2/pld/abc80-1m-ic5.mx b/v1.2/pld/abc80-1m-ic5.mx
new file mode 100644
index 0000000..168ee5a
--- /dev/null
+++ b/v1.2/pld/abc80-1m-ic5.mx
@@ -0,0 +1,122 @@
+Name abc80-1m-ic5 ;
+PartNo 05 ;
+Date 2020-09-05 ;
+Revision 1.1.2 ;
+Designer H. Peter Anvin ;
+Company Self ;
+Assembly abc80-1m-sram ;
+Location IC5 ;
+Device g22v10 ;
+
+/* *************** INPUT PINS *********************/
+PIN 1 = MAPWR; /* implicit register clock */
+PIN 2 = IORQn;
+PIN 3 = BOOTn;
+PIN 4 = A3;
+PIN 5 = RESETn;
+PIN 6 = A2;
+PIN 7 = M1n;
+PIN 8 = RFSHn;
+PIN 9 = MD6;
+PIN 10 = BUFENn;
+PIN 11 = MD4;
+PIN 13 = MD7;
+PIN 14 = A4;
+PIN 21 = NMI_SYSn;
+
+/* *************** OUTPUT PINS *********************/
+PIN 15 = !IOSEL;
+PIN 16 = BYPASSn;
+PIN 17 = ROMMAPn;
+PIN 18 = MA3;
+PIN 19 = IRQDIS;
+PIN 20 = !INT;
+PIN 22 = !NMI;
+PIN 23 = IORQ_SYSn;
+
+true = 'b'1;
+false = 'b'0;
+
+/*
+ * Is this an I/O cycle that could possibly be directed at us?
+ */
+IOSEL = !IORQn & M1n & A2;
+
+/*
+ * Is this an I/O cycle that should be forwarded to the system?
+ * If !M1# and A4=A2=1, suppress the system IORQ#
+ */
+IORQ_SYSn = IORQn # (M1n & A4 & A2);
+
+/*
+ * Interrupt handling:
+ *
+ * NMI# is output low (otherwise high) if:
+ * - NMIIN# is low, AND
+ * - the INT flip flop is 0 (default), AND
+ * - IRQDIS is 0 (default)
+ *
+ * INT# is ouput low (otherwise Z) if:
+ * - the INT flip flop is 1
+ * - IRQDIS is 0
+ *
+ * The INT flip flop is set to 1 by writing 11xxxxxx to the control
+ * register; set to 0 by writing either 01xxxxxx or 10xxxxxx to the
+ * control register.
+ *
+ * IRQDIS is set by writing bit 6 of the control register. This
+ * acts as NMI disable if bit 7 = 0 or as EOI if bit 7 = 1.
+ * IRQEN is clear either by writing 10xxxxxx to the control
+ * register (NMI clock enable) or by NMIIN# low with the INT flip flop set.
+ *
+ * The following commands are thus accepted by the control register:
+ * 00xxxxxx = no change
+ * 01xxxxxx = disable clock
+ * 10xxxxxx = NMI# clock (default)
+ * 11xxxxxx = INT# clock, also EOI
+ */
+
+
+/*
+ * Register set on RESET (output inverted!), clear by writing
+ * a map with IRQEN=1. OE is only enabled if the register is set to
+ * 0, the effect is an open drain output pulsing INT#.
+ */
+INT.AR = !RESETn;
+INT.D = (INT & !MD6 & !MD7) # (MD6 & MD7);
+INT.OE = INT & !IRQDIS;
+inten = INT; /* INT# enabled */
+nmien = !IRQDIS & !INT;
+
+IRQDIS = ( /* Set under these conditions */
+ (MAPWR & MD6)
+ /* ... */
+ # (IRQDIS & !(
+ /* Clear under these conditions */
+ (!RESETn # (MAPWR & MD7 & !MD6) # (inten & !NMI_SYSn))
+ /* ... */
+ )));
+
+NMI = !NMI_SYSn & nmien;
+
+/*
+ * BOOT# is asserted if we are in "system" mode and have not yet
+ * written to the control register. In addition, assert BYPASS#
+ * on IORQ#, RFSH#, or RESET#.
+ *
+ * If BYPASS# is asserted, IC4 will ignore memory accesses and
+ * IC9 will gate A15-A13 onto the system bus untranslated.
+ */
+BYPASSn = BOOTn & IORQn & RFSHn & RESETn;
+
+/*
+ * Register clear on RESET, set by writing a map with ROMMAP=0
+ * Map is ROM if clear, RAM if set.
+ */
+ROMMAPn.AR = !RESETn;
+ROMMAPn.D = !MD4;
+
+/*
+ * A3 control ... equivalent to MUX B and thus controlled by BUFEN#
+ */
+ MA3 = A3 & !BUFENn;
diff --git a/v1.2/pld/abc80-1m-ic5.pdf b/v1.2/pld/abc80-1m-ic5.pdf
new file mode 100644
index 0000000..01c04ed
--- /dev/null
+++ b/v1.2/pld/abc80-1m-ic5.pdf
@@ -0,0 +1,222 @@
+{COMPONENT C:\WINCUPL\PROJECTS\ABC80-1M-SRAM\ABC80-1M-IC5.SYM
+
+ {ENVIRONMENT
+ {PDIFvrev 3.00}
+ {Program "CUPL(WM) Version 5.0a"}
+ {DBtype "Schematic"}
+ {DBvrev 1.01}
+ {DBtime "Sun Sep 06 14:23:02 2020 "}
+ {DBunit "MIL"}
+ {DBgrid 10}
+ {Lyrstr "WIRES" 1 "BUS" 1 "GATE" 2 "IEEE" 2 "PINFUN" 3 "PINNUM" 1
+ "PINNAM" 6 "PINCON" 4 "REFDES" 2 "ATTR" 6 "SDOT" 1
+ "DEVICE" 5 "OUTLIN" 5 "ATTR2" 6 "NOTES" 6 "NETNAM" 4
+ "CMPNAM" 5 "BORDER" 5}
+ }
+
+ {USER
+ {VIEW
+ {Mode SYMB}
+ {Nlst OPEN}
+ {Vw 0 0 2}
+ {Lv 12 2 2 2 0 0 2 2 2 2 0 0 2 1 2 0 0 0 0}
+ {Gs 10 10}
+ }
+ }
+
+ {DISPLAY
+ [Ly "PINNUM"]
+ [Ls "SOLID"][Wd 0]
+ [Ts 15][Tj "LC"][Tr 0][Tm "N"]
+ }
+
+ {SYMBOL
+ {PIN_DEF
+ [Ly "PINCON"]
+ {P MAPWR {Pt "INPUT"}{Lq 0}{Ploc 100 300}}
+ {P IORQN {Pt "INPUT"}{Lq 0}{Ploc 100 260}}
+ {P BOOTN {Pt "INPUT"}{Lq 0}{Ploc 100 240}}
+ {P A3 {Pt "INPUT"}{Lq 0}{Ploc 100 220}}
+ {P RESETN {Pt "INPUT"}{Lq 0}{Ploc 100 200}}
+ {P A2 {Pt "INPUT"}{Lq 0}{Ploc 100 180}}
+ {P M1N {Pt "INPUT"}{Lq 0}{Ploc 100 160}}
+ {P RFSHN {Pt "INPUT"}{Lq 0}{Ploc 100 140}}
+ {P MD6 {Pt "INPUT"}{Lq 0}{Ploc 100 120}}
+ {P BUFENN {Pt "INPUT"}{Lq 0}{Ploc 100 100}}
+ {P MD4 {Pt "INPUT"}{Lq 0}{Ploc 100 80}}
+ {P MD7 {Pt "INPUT"}{Lq 0}{Ploc 100 60}}
+ {P A4 {Pt "INPUT"}{Lq 0}{Ploc 100 40}}
+ {P NMI_SYSN {Pt "INPUT"}{Lq 0}{Ploc 100 20}}
+ {P IOSEL' {Pt "I/O"}{Lq 0}{Ploc 360 20}}
+ {P BYPASSN {Pt "I/O"}{Lq 0}{Ploc 360 40}}
+ {P MA3 {Pt "I/O"}{Lq 0}{Ploc 360 60}}
+ {P IRQDIS {Pt "I/O"}{Lq 0}{Ploc 360 80}}
+ {P NMI' {Pt "I/O"}{Lq 0}{Ploc 360 100}}
+ {P IORQ_SYS {Pt "I/O"}{Lq 0}{Ploc 360 120}}
+ {P ROMMAPN {Pt "OUTPUT"}{Lq 0}{Ploc 360 140}}
+ {P INT' {Pt "OUTPUT"}{Lq 0}{Ploc 360 160}}
+ }
+
+ {PKG
+ [Ly "REFDES"]
+ [Ts 25][Tj "CB"][Tr 0][Tm "N"]
+ {Rdl 230 330}
+
+ [Ly "PINNUM"]
+ [Ts 15][Tj "RC"]
+ {Pnl 120 310}
+ [Ts 15][Tj "RC"]
+ {Pnl 120 270}
+ {Pnl 120 250}
+ {Pnl 120 230}
+ {Pnl 120 210}
+ {Pnl 120 190}
+ {Pnl 120 170}
+ {Pnl 120 150}
+ {Pnl 120 130}
+ {Pnl 120 110}
+ {Pnl 120 90}
+ {Pnl 120 70}
+ {Pnl 120 50}
+ {Pnl 120 30}
+ [Ts 15][Tj "LC"]
+ {Pnl 340 30}
+ {Pnl 340 50}
+ {Pnl 340 70}
+ {Pnl 340 90}
+ {Pnl 340 110}
+ {Pnl 340 130}
+ {Pnl 340 150}
+ {Pnl 340 170}
+
+ {Sd A 1 2 3 4 5 6 7 8 9 10 11 13 14 21 15 16 18 19 22 23 17 20}
+ }
+
+ {PIC
+ [Ly "GATE"]
+ [Ts 15][Tj "LC"][Tr 0][Tm "N"]
+ {R 130 320 330 0}
+ {L 130 300 100 300}
+ {L 130 310 140 300 130 290}
+ {L 130 260 100 260}
+ {L 130 240 100 240}
+ {L 130 220 100 220}
+ {L 130 200 100 200}
+ {L 130 180 100 180}
+ {L 130 160 100 160}
+ {L 130 140 100 140}
+ {L 130 120 100 120}
+ {L 130 100 100 100}
+ {L 130 80 100 80}
+ {L 130 60 100 60}
+ {L 130 40 100 40}
+ {L 130 20 100 20}
+ {C 335 20 5}
+ {L 340 20 360 20}
+ {L 330 40 360 40}
+ {L 330 60 360 60}
+ {L 330 80 360 80}
+ {C 335 100 5}
+ {L 340 100 360 100}
+ {L 330 120 360 120}
+ {L 330 140 360 140}
+ {C 335 160 5}
+ {L 340 160 360 160}
+ [Ly "PINNAM"]
+ [Tj "LC"]
+ {T "MAPWR" 140 300}
+ {T "IORQN" 140 260}
+ {T "BOOTN" 140 240}
+ {T "A3" 140 220}
+ {T "RESETN" 140 200}
+ {T "A2" 140 180}
+ {T "M1N" 140 160}
+ {T "RFSHN" 140 140}
+ {T "MD6" 140 120}
+ {T "BUFENN" 140 100}
+ {T "MD4" 140 80}
+ {T "MD7" 140 60}
+ {T "A4" 140 40}
+ {T "NMI_SYSN" 140 20}
+ [Tj "RC"]
+ {T "IOSEL'" 320 20}
+ {T "BYPASSN" 320 40}
+ {T "MA3" 320 60}
+ {T "IRQDIS" 320 80}
+ {T "NMI'" 320 100}
+ {T "IORQ_SYS" 320 120}
+ {T "ROMMAPN" 320 140}
+ {T "INT'" 320 160}
+ [Ly "DEVICE"]
+ [Tj "CT"]
+ {T "G22V10" 230 -10}
+ }
+
+ {ATR
+ {IN
+ {Org 100 20}
+ {Ty 255}
+ }
+ {EX
+ [Ly "ATTR2"]
+ [Ts 12][Tj "CT"][Tr 0][Tm "N"]
+ {At PLD C:\WINCUPL\PROJECTS\ABC80-1M-SRAM\ABC80-1M-IC5 230 320}
+ }
+ }
+ }
+
+ {DETAIL
+ {ANNOTATE
+ }
+
+ {NET_DEF
+ {N MAPWR
+ }
+ {N IORQN
+ }
+ {N BOOTN
+ }
+ {N A3
+ }
+ {N RESETN
+ }
+ {N A2
+ }
+ {N M1N
+ }
+ {N RFSHN
+ }
+ {N MD6
+ }
+ {N BUFENN
+ }
+ {N MD4
+ }
+ {N MD7
+ }
+ {N A4
+ }
+ {N NMI_SYSN
+ }