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* pld/ic5: assert BYPASS# during RESET#H. Peter Anvin2020-09-069-43/+52
* pld/ic4: fix inverted condition for ACLR#H. Peter Anvin2020-09-069-24/+24
* pld/ic4: fix OE#, timing of various control signalsH. Peter Anvin2020-09-069-314/+314
* pld/ic5: fix logic for IORQ_SYS#H. Peter Anvin2020-09-059-102/+105
* PLD: downcase filenamesH. Peter Anvin2020-08-2225-0/+92
* Fix WinCUPL polarity brain damageH. Peter Anvin2020-08-229-62/+49
* IC5: update to match MAPWR being a positive pulseH. Peter Anvin2020-08-229-42/+42
* PLD: make MAPWR a synchronous signalH. Peter Anvin2020-08-228-121/+146
* PLD implementation. Fix MD5 -> MD4 for IC5, and make BOOT# reflect modeH. Peter Anvin2020-08-2226-706/+2235
* Polarity and bug fixesH. Peter Anvin2020-08-1618-1117/+433
* pld/ic5: INT# is level sensitiveH. Peter Anvin2020-08-159-162/+285
* pld/ic5: make BOOT# open drainH. Peter Anvin2020-08-159-135/+179
* Rename some objects; PLD definitions & outputH. Peter Anvin2020-08-1318-0/+1947