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authorH. Peter Anvin <hpa@zytor.com>2021-02-22 15:57:25 -0800
committerH. Peter Anvin <hpa@zytor.com>2021-02-22 15:57:25 -0800
commit4c4ff56316f18036f723472b93c45f2406741742 (patch)
tree9e9ee20cd0a22733916d08736017b0fa528120f5
parent6c70e250b97de7e0331242ce565300222869a36d (diff)
downloadfpga-template-master.tar.gz
fpga-template-master.tar.xz
fpga-template-master.zip
Update pinout after sr_a[5] and sd_cmd move; abc_800 still unassignedHEADmaster
-rw-r--r--max80.qsf1
-rw-r--r--output_files/max80.fit.rpt71
-rw-r--r--output_files/max80.pin8
3 files changed, 39 insertions, 41 deletions
diff --git a/max80.qsf b/max80.qsf
index db9c8fa..66f330b 100644
--- a/max80.qsf
+++ b/max80.qsf
@@ -185,7 +185,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_location_assignment PIN_97 -to spi_cs_flash_n
-set_location_assignment PIN_88 -to abc_800
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to sr_clk
set_location_assignment PIN_80 -to abc_rdy_n
diff --git a/output_files/max80.fit.rpt b/output_files/max80.fit.rpt
index 1994eb2..0c4ef30 100644
--- a/output_files/max80.fit.rpt
+++ b/output_files/max80.fit.rpt
@@ -1,5 +1,5 @@
Fitter report for max80
-Mon Feb 22 15:40:17 2021
+Mon Feb 22 15:56:31 2021
Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
@@ -69,7 +69,7 @@ https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Mon Feb 22 15:40:17 2021 ;
+; Fitter Status ; Successful - Mon Feb 22 15:56:31 2021 ;
; Quartus Prime Version ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
; Revision Name ; max80 ;
; Top-level Entity Name ; max80 ;
@@ -252,7 +252,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/fpga-template/output_file
; Oscillator blocks ; 0 / 1 ( 0 % ) ;
; Impedance control blocks ; 0 / 1 ( 0 % ) ;
; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
-; Peak interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.1% ;
+; Peak interconnect usage (total/H/V) ; 0.1% / 0.1% / 0.1% ;
; Maximum fan-out ; 16 ;
; Highest non-global fan-out ; 13 ;
; Total fan-out ; 228 ;
@@ -340,7 +340,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/fpga-template/output_file
+-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
+-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
-; abc_800 ; 88 ; 6 ; 50 ; 14 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
+; abc_800 ; 24 ; 1B ; 0 ; 11 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; Fitter ; 0 ;
; abc_clk ; 90 ; 6 ; 50 ; 15 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
; abc_iord_n ; 131 ; 8 ; 12 ; 17 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
; abc_iowr_n ; 130 ; 8 ; 12 ; 17 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
@@ -371,7 +371,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/fpga-template/output_file
; led[2] ; 17 ; 1B ; 0 ; 14 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
; led[3] ; 14 ; 1A ; 25 ; 22 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
; sd_clk ; 48 ; 3 ; 16 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
-; sd_cmd ; 41 ; 3 ; 6 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sd_cmd ; 88 ; 6 ; 50 ; 14 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
; sr_a[0] ; 89 ; 6 ; 50 ; 14 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
; sr_a[10] ; 91 ; 6 ; 50 ; 15 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
; sr_a[11] ; 47 ; 3 ; 14 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
@@ -380,7 +380,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/fpga-template/output_file
; sr_a[2] ; 86 ; 5 ; 50 ; 11 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
; sr_a[3] ; 85 ; 5 ; 50 ; 11 ; 22 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
; sr_a[4] ; 74 ; 5 ; 50 ; 2 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
-; sr_a[5] ; 126 ; 8 ; 14 ; 17 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; Fitter ; - ; - ;
+; sr_a[5] ; 41 ; 3 ; 6 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
; sr_a[6] ; 43 ; 3 ; 6 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
; sr_a[7] ; 44 ; 3 ; 8 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
; sr_a[8] ; 45 ; 3 ; 8 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
@@ -464,7 +464,6 @@ The pin-out file can be found in /home/hpa/abc80/max80/fpga-template/output_file
; 20 ; DIFFIO_RX_L12p, DIFFOUT_L12p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ;
; 121 ; DIFFIO_RX_T28n, DIFFOUT_T28n, DEV_CLRn, Low_Speed ; Use as regular IO ; abc_ad[0] ; Dual Purpose Pin ;
; 122 ; DEV_OE ; Use as regular IO ; abc_xm_n ; Dual Purpose Pin ;
-; 126 ; CONFIG_SEL, Low_Speed ; Use as regular IO ; sr_a[5] ; Dual Purpose Pin ;
; 134 ; DIFFIO_RX_T34n, DIFFOUT_T34n, CRC_ERROR, Low_Speed ; Use as regular IO ; abc_adsel[1] ; Dual Purpose Pin ;
; 138 ; DIFFIO_RX_T36n, DIFFOUT_T36n, CONF_DONE, Low_Speed ; Use as regular IO ; tty_cts ; Dual Purpose Pin ;
+----------+----------------------------------------------------+--------------------------------+------------------+------------------+
@@ -476,14 +475,14 @@ The pin-out file can be found in /home/hpa/abc80/max80/fpga-template/output_file
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+-------------------+---------------+--------------+
; 1A ; 8 / 8 ( 100 % ) ; 3.3V ; -- ;
-; 1B ; 9 / 10 ( 90 % ) ; 3.3V ; -- ;
+; 1B ; 10 / 10 ( 100 % ) ; 3.3V ; -- ;
; 2 ; 7 / 7 ( 100 % ) ; 3.3V ; -- ;
; 3 ; 18 / 18 ( 100 % ) ; 3.3V ; -- ;
; 4 ; 7 / 7 ( 100 % ) ; 3.3V ; -- ;
; 5 ; 12 / 12 ( 100 % ) ; 3.3V ; -- ;
; 6 ; 15 / 15 ( 100 % ) ; 3.3V ; -- ;
; 7 ; 6 / 7 ( 86 % ) ; 3.3V ; -- ;
-; 8 ; 15 / 17 ( 88 % ) ; 3.3V ; -- ;
+; 8 ; 14 / 17 ( 82 % ) ; 3.3V ; -- ;
+----------+-------------------+---------------+--------------+
@@ -515,7 +514,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/fpga-template/output_file
; 21 ; 28 ; 1B ; spi_miso ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 22 ; 30 ; 1B ; spi_mosi ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 23 ; ; 1B ; VCCIO1B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 24 ; 32 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; 24 ; 32 ; 1B ; abc_800 ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
; 25 ; 34 ; 1B ; spi_clk ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 26 ; 40 ; 2 ; clock_48 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 27 ; 42 ; 2 ; rtc_32khz ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
@@ -532,7 +531,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/fpga-template/output_file
; 38 ; 68 ; 3 ; sd_dat[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 39 ; 70 ; 3 ; sd_dat[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 40 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 41 ; 72 ; 3 ; sd_cmd ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 41 ; 72 ; 3 ; sr_a[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 42 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 43 ; 74 ; 3 ; sr_a[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 44 ; 76 ; 3 ; sr_a[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
@@ -579,7 +578,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/fpga-template/output_file
; 85 ; 184 ; 5 ; sr_a[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 86 ; 187 ; 5 ; sr_a[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 87 ; 186 ; 5 ; sr_a[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
-; 88 ; 192 ; 6 ; abc_800 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 88 ; 192 ; 6 ; sd_cmd ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 89 ; 194 ; 6 ; sr_a[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 90 ; 196 ; 6 ; abc_clk ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
; 91 ; 198 ; 6 ; sr_a[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
@@ -617,7 +616,7 @@ The pin-out file can be found in /home/hpa/abc80/max80/fpga-template/output_file
; 123 ; 299 ; 8 ; abc_memwr_n ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 124 ; 301 ; 8 ; abc_int_n ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 125 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 126 ; 300 ; 8 ; sr_a[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; On ;
+; 126 ; 300 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
; 127 ; 303 ; 8 ; abc_resin ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
; 128 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 129 ; 302 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
@@ -776,7 +775,7 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
; gpio[4] ; Missing drive strength ;
; gpio[5] ; Missing drive strength ;
; gpio_jtagen ; Missing drive strength ;
-; sr_a[5] ; Missing location assignment ;
+; abc_800 ; Missing location assignment ;
+----------------+-----------------------------+
@@ -987,14 +986,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Routing Resource Type ; Usage ;
+-----------------------+-----------------------+
; Block interconnects ; 9 / 49,625 ( < 1 % ) ;
-; C16 interconnects ; 0 / 2,250 ( 0 % ) ;
-; C4 interconnects ; 7 / 39,600 ( < 1 % ) ;
+; C16 interconnects ; 1 / 2,250 ( < 1 % ) ;
+; C4 interconnects ; 6 / 39,600 ( < 1 % ) ;
; Direct links ; 5 / 49,625 ( < 1 % ) ;
; Global clocks ; 1 / 20 ( 5 % ) ;
; Local interconnects ; 16 / 15,840 ( < 1 % ) ;
; NSLEEPs ; 0 / 320 ( 0 % ) ;
; R24 interconnects ; 0 / 2,146 ( 0 % ) ;
-; R4 interconnects ; 4 / 53,244 ( < 1 % ) ;
+; R4 interconnects ; 6 / 53,244 ( < 1 % ) ;
+-----------------------+-----------------------+
@@ -1162,7 +1161,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; abc_nmi ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; abc_int_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; abc_xm_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; abc_800 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_800 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; sr_clk ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; sr_cke ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; sr_ba[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
@@ -1172,7 +1171,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; sr_a[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; sr_a[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; sr_a[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
-; sr_a[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_a[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; sr_a[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; sr_a[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
; sr_a[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
@@ -1361,32 +1360,32 @@ Info (332110): Deriving PLL clocks
Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[0]} {pll|altpll_component|auto_generated|pll1|clk[0]}
Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[1]} {pll|altpll_component|auto_generated|pll1|clk[1]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
-Warning (332174): Ignored filter at max80.sdc(29): *|synchronizer:*|qreg0* could not be matched with a register File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 29
-Warning (332049): Ignored set_multicycle_path at max80.sdc(30): Argument <to> is an empty collection File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 30
+Warning (332174): Ignored filter at max80.sdc(30): *|synchronizer:*|qreg0* could not be matched with a register File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 30
+Warning (332049): Ignored set_multicycle_path at max80.sdc(31): Argument <to> is an empty collection File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 31
Info (332050): set_multicycle_path -from [all_clocks] -to $synchro_inputs \
- -start -setup 2 File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 30
-Warning (332049): Ignored set_multicycle_path at max80.sdc(32): Argument <to> is an empty collection File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 32
+ -start -setup 2 File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 31
+Warning (332049): Ignored set_multicycle_path at max80.sdc(33): Argument <to> is an empty collection File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 33
Info (332050): set_multicycle_path -from [all_clocks] -to $synchro_inputs \
- -start -hold -1 File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 32
-Warning (332174): Ignored filter at max80.sdc(36): sld_signaltap:* could not be matched with a register File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 36
-Warning (332049): Ignored set_false_path at max80.sdc(36): Argument <to> is an empty collection File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 36
- Info (332050): set_false_path -to [get_registers sld_signaltap:*] File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 36
+ -start -hold -1 File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 33
+Warning (332174): Ignored filter at max80.sdc(37): sld_signaltap:* could not be matched with a register File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 37
+Warning (332049): Ignored set_false_path at max80.sdc(37): Argument <to> is an empty collection File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 37
+ Info (332050): set_false_path -to [get_registers sld_signaltap:*] File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 37
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 5 clocks
Info (332111): Period Clock Name
Info (332111): ======== ============
- Info (332111): 20.833 clock_48
+ Info (332111): 20.834 clock_48
Info (332111): 6.944 pll|altpll_component|auto_generated|pll1|clk[0]
- Info (332111): 10.416 pll|altpll_component|auto_generated|pll1|clk[1]
- Info (332111): 10.416 rst_n
- Info (332111): 30517.000 rtc_32khz
+ Info (332111): 10.417 pll|altpll_component|auto_generated|pll1|clk[1]
+ Info (332111): 10.417 rst_n
+ Info (332111): 30517.579 rtc_32khz
Info (176233): Starting register packing
Info (176221): The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os.
Info (176235): Finished register packing
Extra Info (176219): No registers were packed into other blocks
Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
- Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
+ Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 1 input, 0 output, 0 bidirectional)
Info (176212): I/O standards used: 3.3-V LVTTL.
Info (176215): I/O bank details before I/O pin placement
Info (176214): Statistics of I/O banks
@@ -1414,7 +1413,7 @@ Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were
Info (170201): Optimizations that may affect the design's routability were skipped
Info (170200): Optimizations that may affect the design's timing were skipped
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.04 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds.
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (334003): Started post-fitting delay annotation
@@ -1426,7 +1425,7 @@ Warning (169177): 56 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and
Info (169178): Pin abc_memrd_n uses I/O standard 3.3-V LVTTL at 132 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 18
Info (169178): Pin abc_iowr_n uses I/O standard 3.3-V LVTTL at 130 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 19
Info (169178): Pin abc_iord_n uses I/O standard 3.3-V LVTTL at 131 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 20
- Info (169178): Pin abc_800 uses I/O standard 3.3-V LVTTL at 88 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 26
+ Info (169178): Pin abc_800 uses I/O standard 3.3-V LVTTL at 24 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 26
Info (169178): Pin tty_txd uses I/O standard 3.3-V LVTTL at 55 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 46
Info (169178): Pin tty_rts uses I/O standard 3.3-V LVTTL at 106 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 48
Info (169178): Pin tty_dtr uses I/O standard 3.3-V LVTTL at 140 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 50
@@ -1524,8 +1523,8 @@ Warning (169064): Following 44 pins have no output enable or a GND or VCC output
Info (169065): Pin gpio_jtagen has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 85
Info (144001): Generated suppressed messages file /home/hpa/abc80/max80/fpga-template/output_files/max80.fit.smsg
Info: Quartus Prime Fitter was successful. 0 errors, 20 warnings
- Info: Peak virtual memory: 1403 megabytes
- Info: Processing ended: Mon Feb 22 15:40:17 2021
+ Info: Peak virtual memory: 1405 megabytes
+ Info: Processing ended: Mon Feb 22 15:56:32 2021
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:08
diff --git a/output_files/max80.pin b/output_files/max80.pin
index 5fdb368..f53b5d9 100644
--- a/output_files/max80.pin
+++ b/output_files/max80.pin
@@ -93,7 +93,7 @@ led[2] : 17 : output : 3.3-V LVTTL :
spi_miso : 21 : bidir : 3.3-V LVTTL : : 1B : Y
spi_mosi : 22 : bidir : 3.3-V LVTTL : : 1B : Y
VCCIO1B : 23 : power : : 3.3V : 1B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : 24 : : : : 1B :
+abc_800 : 24 : input : 3.3-V LVTTL : : 1B : N
spi_clk : 25 : bidir : 3.3-V LVTTL : : 1B : Y
clock_48 : 26 : input : 3.3-V LVTTL : : 2 : Y
rtc_32khz : 27 : input : 3.3-V LVTTL : : 2 : Y
@@ -110,7 +110,7 @@ VCC_ONE : 37 : power : : 3.0V/3.3
sd_dat[2] : 38 : bidir : 3.3-V LVTTL : : 3 : Y
sd_dat[3] : 39 : bidir : 3.3-V LVTTL : : 3 : Y
VCCIO3 : 40 : power : : 3.3V : 3 :
-sd_cmd : 41 : output : 3.3-V LVTTL : : 3 : Y
+sr_a[5] : 41 : output : 3.3-V LVTTL : : 3 : Y
GND : 42 : gnd : : : :
sr_a[6] : 43 : output : 3.3-V LVTTL : : 3 : Y
sr_a[7] : 44 : output : 3.3-V LVTTL : : 3 : Y
@@ -157,7 +157,7 @@ sr_dq[5] : 84 : bidir : 3.3-V LVTTL :
sr_a[3] : 85 : output : 3.3-V LVTTL : : 5 : Y
sr_a[2] : 86 : output : 3.3-V LVTTL : : 5 : Y
sr_a[1] : 87 : output : 3.3-V LVTTL : : 5 : Y
-abc_800 : 88 : input : 3.3-V LVTTL : : 6 : Y
+sd_cmd : 88 : output : 3.3-V LVTTL : : 6 : Y
sr_a[0] : 89 : output : 3.3-V LVTTL : : 6 : Y
abc_clk : 90 : input : 3.3-V LVTTL : : 6 : Y
sr_a[10] : 91 : output : 3.3-V LVTTL : : 6 : Y
@@ -195,7 +195,7 @@ abc_xm_n : 122 : output : 3.3-V LVTTL :
abc_memwr_n : 123 : input : 3.3-V LVTTL : : 8 : Y
abc_int_n : 124 : output : 3.3-V LVTTL : : 8 : Y
GND : 125 : gnd : : : :
-sr_a[5] : 126 : output : 3.3-V LVTTL : : 8 : N
+RESERVED_INPUT_WITH_WEAK_PULLUP : 126 : : : : 8 :
abc_resin : 127 : output : 3.3-V LVTTL : : 8 : Y
VCCIO8 : 128 : power : : 3.3V : 8 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 129 : : : : 8 :