diff options
| author | H. Peter Anvin <hpa@zytor.com> | 2021-02-22 15:49:39 -0800 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2021-02-22 15:49:39 -0800 |
| commit | 6c70e250b97de7e0331242ce565300222869a36d (patch) | |
| tree | c7ea1b857247225c0657fc07b39780ec6b462226 /ip/pll.qip | |
| download | fpga-template-6c70e250b97de7e0331242ce565300222869a36d.tar.gz fpga-template-6c70e250b97de7e0331242ce565300222869a36d.tar.xz fpga-template-6c70e250b97de7e0331242ce565300222869a36d.zip | |
Update pinout; now compiles
Diffstat (limited to 'ip/pll.qip')
| -rw-r--r-- | ip/pll.qip | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/ip/pll.qip b/ip/pll.qip new file mode 100644 index 0000000..6161b54 --- /dev/null +++ b/ip/pll.qip @@ -0,0 +1,8 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_bb.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] |