summaryrefslogtreecommitdiffstats
path: root/output_files
diff options
context:
space:
mode:
authorH. Peter Anvin <hpa@zytor.com>2021-02-22 15:49:39 -0800
committerH. Peter Anvin <hpa@zytor.com>2021-02-22 15:49:39 -0800
commit6c70e250b97de7e0331242ce565300222869a36d (patch)
treec7ea1b857247225c0657fc07b39780ec6b462226 /output_files
downloadfpga-template-6c70e250b97de7e0331242ce565300222869a36d.tar.gz
fpga-template-6c70e250b97de7e0331242ce565300222869a36d.tar.xz
fpga-template-6c70e250b97de7e0331242ce565300222869a36d.zip
Update pinout; now compiles
Diffstat (limited to 'output_files')
-rw-r--r--output_files/max80.fit.rpt1538
-rw-r--r--output_files/max80.pin216
2 files changed, 1754 insertions, 0 deletions
diff --git a/output_files/max80.fit.rpt b/output_files/max80.fit.rpt
new file mode 100644
index 0000000..1994eb2
--- /dev/null
+++ b/output_files/max80.fit.rpt
@@ -0,0 +1,1538 @@
+Fitter report for max80
+Mon Feb 22 15:40:17 2021
+Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. Parallel Compilation
+ 5. Incremental Compilation Preservation Summary
+ 6. Incremental Compilation Partition Settings
+ 7. Incremental Compilation Placement Preservation
+ 8. Pin-Out File
+ 9. Fitter Resource Usage Summary
+ 10. Fitter Partition Statistics
+ 11. Input Pins
+ 12. Output Pins
+ 13. Bidir Pins
+ 14. Dual Purpose and Dedicated Pins
+ 15. I/O Bank Usage
+ 16. All Package Pins
+ 17. PLL Summary
+ 18. PLL Usage
+ 19. I/O Assignment Warnings
+ 20. Fitter Resource Utilization by Entity
+ 21. Delay Chain Summary
+ 22. Pad To Core Delay Chain Fanout
+ 23. Control Signals
+ 24. Global & Other Fast Signals
+ 25. Routing Usage Summary
+ 26. LAB Logic Elements
+ 27. LAB-wide Signals
+ 28. LAB Signals Sourced
+ 29. LAB Signals Sourced Out
+ 30. LAB Distinct Inputs
+ 31. I/O Rules Summary
+ 32. I/O Rules Details
+ 33. I/O Rules Matrix
+ 34. Fitter Device Options
+ 35. Operating Settings and Conditions
+ 36. Fitter Messages
+ 37. Fitter Suppressed Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 2019 Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+
+
+
++----------------------------------------------------------------------------------+
+; Fitter Summary ;
++------------------------------------+---------------------------------------------+
+; Fitter Status ; Successful - Mon Feb 22 15:40:17 2021 ;
+; Quartus Prime Version ; 18.1.1 Build 646 04/11/2019 SJ Lite Edition ;
+; Revision Name ; max80 ;
+; Top-level Entity Name ; max80 ;
+; Family ; MAX 10 ;
+; Device ; 10M16SCE144C8G ;
+; Timing Models ; Final ;
+; Total logic elements ; 20 / 15,840 ( < 1 % ) ;
+; Total combinational functions ; 20 / 15,840 ( < 1 % ) ;
+; Dedicated logic registers ; 13 / 15,840 ( < 1 % ) ;
+; Total registers ; 13 ;
+; Total pins ; 93 / 101 ( 92 % ) ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 / 562,176 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 90 ( 0 % ) ;
+; Total PLLs ; 1 / 1 ( 100 % ) ;
+; UFM blocks ; 0 / 1 ( 0 % ) ;
+; ADC blocks ; 0 ;
++------------------------------------+---------------------------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++--------------------------------------------------------------------+-------------------------------------------------------------+---------------------------------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------------+-------------------------------------------------------------+---------------------------------------+
+; Device ; 10M16SCE144C8G ; ;
+; Nominal Core Supply Voltage ; 3.3V ; ;
+; Minimum Core Junction Temperature ; 0 ; ;
+; Maximum Core Junction Temperature ; 85 ; ;
+; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Device Migration List ; 10M16SCE144C8G,10M08SCE144C8G,10M04SCE144C8G,10M25SCE144C8G ; ;
+; Device I/O Standard ; 3.3-V LVTTL ; ;
+; Optimize IOC Register Placement for Timing ; Pack All IO Registers ; Normal ;
+; Weak Pull-Up Resistor ; On ; Off ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Auto Merge PLLs ; On ; On ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Router Effort Multiplier ; 1.0 ; 1.0 ;
+; Optimize Hold Timing ; All Paths ; All Paths ;
+; Optimize Multi-Corner Timing ; On ; On ;
+; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
+; SSN Optimization ; Off ; Off ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
+; PCI I/O ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
+; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
+; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
+; Auto Register Duplication ; Auto ; Auto ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
+; Synchronizer Identification ; Auto ; Auto ;
+; Enable Beneficial Skew Optimization ; On ; On ;
+; Optimize Design for Metastability ; On ; On ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
++--------------------------------------------------------------------+-------------------------------------------------------------+---------------------------------------+
+
+
++------------------------------------------+
+; Parallel Compilation ;
++----------------------------+-------------+
+; Processors ; Number ;
++----------------------------+-------------+
+; Number detected on machine ; 4 ;
+; Maximum allowed ; 2 ;
+; ; ;
+; Average used ; 1.00 ;
+; Maximum used ; 2 ;
+; ; ;
+; Usage by Processor ; % Time Used ;
+; Processor 1 ; 100.0% ;
+; Processor 2 ; 0.2% ;
++----------------------------+-------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
++---------------------+--------------------+----------------------------+--------------------------+
+; Placement (by node) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 277 ) ; 0.00 % ( 0 / 277 ) ; 0.00 % ( 0 / 277 ) ;
+; -- Achieved ; 0.00 % ( 0 / 277 ) ; 0.00 % ( 0 / 277 ) ; 0.00 % ( 0 / 277 ) ;
+; ; ; ; ;
+; Routing (by net) ; ; ; ;
+; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
+; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
++---------------------+--------------------+----------------------------+--------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+; Top ; 0.00 % ( 0 / 260 ) ; N/A ; Source File ; N/A ; ;
+; hard_block:auto_generated_inst ; 0.00 % ( 0 / 17 ) ; N/A ; Source File ; N/A ; ;
++--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in /home/hpa/abc80/max80/fpga-template/output_files/max80.pin.
+
+
++---------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+-----------------------+
+; Resource ; Usage ;
++---------------------------------------------+-----------------------+
+; Total logic elements ; 20 / 15,840 ( < 1 % ) ;
+; -- Combinational with no register ; 7 ;
+; -- Register only ; 0 ;
+; -- Combinational with a register ; 13 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 2 ;
+; -- 3 input functions ; 1 ;
+; -- <=2 input functions ; 17 ;
+; -- Register only ; 0 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 8 ;
+; -- arithmetic mode ; 12 ;
+; ; ;
+; Total registers* ; 13 / 16,318 ( < 1 % ) ;
+; -- Dedicated logic registers ; 13 / 15,840 ( < 1 % ) ;
+; -- I/O registers ; 0 / 478 ( 0 % ) ;
+; ; ;
+; Total LABs: partially or completely used ; 3 / 990 ( < 1 % ) ;
+; Virtual pins ; 0 ;
+; I/O pins ; 93 / 101 ( 92 % ) ;
+; -- Clock pins ; 4 / 4 ( 100 % ) ;
+; -- Dedicated input pins ; 0 / 1 ( 0 % ) ;
+; ; ;
+; M9Ks ; 0 / 61 ( 0 % ) ;
+; UFM blocks ; 0 / 1 ( 0 % ) ;
+; Total block memory bits ; 0 / 562,176 ( 0 % ) ;
+; Total block memory implementation bits ; 0 / 562,176 ( 0 % ) ;
+; Embedded Multiplier 9-bit elements ; 0 / 90 ( 0 % ) ;
+; PLLs ; 1 / 1 ( 100 % ) ;
+; Global signals ; 1 ;
+; -- Global clocks ; 1 / 20 ( 5 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Remote update blocks ; 0 / 1 ( 0 % ) ;
+; Oscillator blocks ; 0 / 1 ( 0 % ) ;
+; Impedance control blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.0% ;
+; Peak interconnect usage (total/H/V) ; 0.0% / 0.0% / 0.1% ;
+; Maximum fan-out ; 16 ;
+; Highest non-global fan-out ; 13 ;
+; Total fan-out ; 228 ;
+; Average fan-out ; 0.82 ;
++---------------------------------------------+-----------------------+
+* Register count does not include registers inside RAM blocks or DSP blocks.
+
+
+
++-----------------------------------------------------------------------------------------------------+
+; Fitter Partition Statistics ;
++---------------------------------------------+----------------------+--------------------------------+
+; Statistic ; Top ; hard_block:auto_generated_inst ;
++---------------------------------------------+----------------------+--------------------------------+
+; Difficulty Clustering Region ; Low ; Low ;
+; ; ; ;
+; Total logic elements ; 15 / 15840 ( < 1 % ) ; 5 / 15840 ( < 1 % ) ;
+; -- Combinational with no register ; 2 ; 5 ;
+; -- Register only ; 0 ; 0 ;
+; -- Combinational with a register ; 13 ; 0 ;
+; ; ; ;
+; Logic element usage by number of LUT inputs ; ; ;
+; -- 4 input functions ; 0 ; 2 ;
+; -- 3 input functions ; 1 ; 0 ;
+; -- <=2 input functions ; 14 ; 3 ;
+; -- Register only ; 0 ; 0 ;
+; ; ; ;
+; Logic elements by mode ; ; ;
+; -- normal mode ; 3 ; 5 ;
+; -- arithmetic mode ; 12 ; 0 ;
+; ; ; ;
+; Total registers ; 13 ; 0 ;
+; -- Dedicated logic registers ; 13 / 15840 ( < 1 % ) ; 0 / 15840 ( 0 % ) ;
+; -- I/O registers ; 0 ; 0 ;
+; ; ; ;
+; Total LABs: partially or completely used ; 3 / 990 ( < 1 % ) ; 1 / 990 ( < 1 % ) ;
+; ; ; ;
+; Virtual pins ; 0 ; 0 ;
+; I/O pins ; 93 ; 0 ;
+; Embedded Multiplier 9-bit elements ; 0 / 90 ( 0 % ) ; 0 / 90 ( 0 % ) ;
+; Total memory bits ; 0 ; 0 ;
+; Total RAM block bits ; 0 ; 0 ;
+; PLL ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;
+; Clock control block ; 0 / 24 ( 0 % ) ; 2 / 24 ( 8 % ) ;
+; User Flash Memory ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ;
+; Analog-to-Digital Converter ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ;
+; ; ; ;
+; Connections ; ; ;
+; -- Input Connections ; 71 ; 4 ;
+; -- Registered Input Connections ; 26 ; 0 ;
+; -- Output Connections ; 48 ; 27 ;
+; -- Registered Output Connections ; 0 ; 0 ;
+; ; ; ;
+; Internal Connections ; ; ;
+; -- Total Connections ; 217 ; 50 ;
+; -- Registered Connections ; 40 ; 0 ;
+; ; ; ;
+; External Connections ; ; ;
+; -- Top ; 88 ; 31 ;
+; -- hard_block:auto_generated_inst ; 31 ; 0 ;
+; ; ; ;
+; Partition Interface ; ; ;
+; -- Input Ports ; 12 ; 4 ;
+; -- Output Ports ; 37 ; 3 ;
+; -- Bidir Ports ; 44 ; 0 ;
+; ; ; ;
+; Registered Ports ; ; ;
+; -- Registered Input Ports ; 0 ; 0 ;
+; -- Registered Output Ports ; 0 ; 0 ;
+; ; ; ;
+; Port Connectivity ; ; ;
+; -- Input Ports driven by GND ; 0 ; 3 ;
+; -- Output Ports driven by GND ; 0 ; 0 ;
+; -- Input Ports driven by VCC ; 0 ; 0 ;
+; -- Output Ports driven by VCC ; 0 ; 0 ;
+; -- Input Ports with no Source ; 0 ; 0 ;
+; -- Output Ports with no Source ; 0 ; 0 ;
+; -- Input Ports with no Fanout ; 0 ; 2 ;
+; -- Output Ports with no Fanout ; 0 ; 0 ;
++---------------------------------------------+----------------------+--------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
+; abc_800 ; 88 ; 6 ; 50 ; 14 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
+; abc_clk ; 90 ; 6 ; 50 ; 15 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
+; abc_iord_n ; 131 ; 8 ; 12 ; 17 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
+; abc_iowr_n ; 130 ; 8 ; 12 ; 17 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
+; abc_memrd_n ; 132 ; 8 ; 12 ; 17 ; 28 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
+; abc_memwr_n ; 123 ; 8 ; 14 ; 17 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
+; clock_48 ; 26 ; 2 ; 0 ; 9 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
+; rtc_32khz ; 27 ; 2 ; 0 ; 9 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
+; rtc_int_n ; 141 ; 8 ; 8 ; 17 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
+; tty_dtr ; 140 ; 8 ; 8 ; 17 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
+; tty_rts ; 106 ; 6 ; 50 ; 26 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
+; tty_txd ; 55 ; 3 ; 21 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; yes ; no ; On ; 3.3-V LVTTL ; -- ; User ; 0 ;
++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+; abc_adsel[0] ; 135 ; 8 ; 10 ; 17 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; abc_adsel[1] ; 134 ; 8 ; 10 ; 17 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; abc_int_n ; 124 ; 8 ; 14 ; 17 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; abc_nmi ; 78 ; 5 ; 50 ; 8 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; abc_rdy_n ; 80 ; 5 ; 50 ; 8 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; abc_resin ; 127 ; 8 ; 14 ; 17 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; abc_xm_n ; 122 ; 8 ; 16 ; 17 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; led[1] ; 30 ; 2 ; 0 ; 7 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; led[2] ; 17 ; 1B ; 0 ; 14 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; led[3] ; 14 ; 1A ; 25 ; 22 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sd_clk ; 48 ; 3 ; 16 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sd_cmd ; 41 ; 3 ; 6 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_a[0] ; 89 ; 6 ; 50 ; 14 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_a[10] ; 91 ; 6 ; 50 ; 15 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_a[11] ; 47 ; 3 ; 14 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_a[12] ; 50 ; 3 ; 16 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_a[1] ; 87 ; 5 ; 50 ; 11 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_a[2] ; 86 ; 5 ; 50 ; 11 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_a[3] ; 85 ; 5 ; 50 ; 11 ; 22 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_a[4] ; 74 ; 5 ; 50 ; 2 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_a[5] ; 126 ; 8 ; 14 ; 17 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; Fitter ; - ; - ;
+; sr_a[6] ; 43 ; 3 ; 6 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_a[7] ; 44 ; 3 ; 8 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_a[8] ; 45 ; 3 ; 8 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_a[9] ; 46 ; 3 ; 14 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_ba[0] ; 93 ; 6 ; 50 ; 16 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_ba[1] ; 92 ; 6 ; 50 ; 16 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_cas_n ; 99 ; 6 ; 50 ; 22 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_cke ; 52 ; 3 ; 16 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_clk ; 33 ; 2 ; 0 ; 3 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_cs_n ; 96 ; 6 ; 50 ; 21 ; 22 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_dqm[0] ; 101 ; 6 ; 50 ; 22 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_dqm[1] ; 56 ; 3 ; 21 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_ras_n ; 98 ; 6 ; 50 ; 21 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; sr_we_n ; 100 ; 6 ; 50 ; 22 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; tty_cts ; 138 ; 8 ; 10 ; 17 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
+; tty_rxd ; 32 ; 2 ; 0 ; 3 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; - ; - ;
++--------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Bidir Pins ;
++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Location assigned by ; Output Enable Source ; Output Enable Group ;
++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
+; abc_ad[0] ; 121 ; 8 ; 19 ; 17 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; abc_ad[1] ; 120 ; 8 ; 19 ; 17 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; abc_ad[2] ; 119 ; 7 ; 28 ; 30 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; abc_ad[3] ; 118 ; 7 ; 30 ; 30 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; abc_ad[4] ; 114 ; 7 ; 38 ; 30 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; abc_ad[5] ; 113 ; 7 ; 38 ; 30 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; abc_ad[6] ; 111 ; 7 ; 48 ; 30 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; abc_ad[7] ; 110 ; 7 ; 48 ; 30 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; esp_int ; 6 ; 1A ; 25 ; 25 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; esp_io0 ; 28 ; 2 ; 0 ; 8 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; gpio[0] ; 13 ; 1A ; 25 ; 22 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; gpio[1] ; 12 ; 1A ; 25 ; 23 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; gpio[2] ; 11 ; 1A ; 25 ; 23 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; gpio[3] ; 10 ; 1A ; 25 ; 24 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; gpio[4] ; 8 ; 1A ; 25 ; 24 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; gpio[5] ; 7 ; 1A ; 25 ; 25 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; gpio_jtagen ; 15 ; 1B ; 0 ; 15 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; i2c_scl ; 61 ; 4 ; 34 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; i2c_sda ; 62 ; 4 ; 34 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sd_dat[0] ; 54 ; 3 ; 19 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sd_dat[1] ; 66 ; 4 ; 41 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sd_dat[2] ; 38 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sd_dat[3] ; 39 ; 3 ; 6 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; spi_clk ; 25 ; 1B ; 0 ; 11 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; spi_cs_esp_n ; 29 ; 2 ; 0 ; 8 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; spi_cs_flash_n ; 97 ; 6 ; 50 ; 21 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; spi_miso ; 21 ; 1B ; 0 ; 12 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; spi_mosi ; 22 ; 1B ; 0 ; 12 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[0] ; 75 ; 5 ; 50 ; 2 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[10] ; 59 ; 3 ; 24 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[11] ; 60 ; 3 ; 24 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[12] ; 64 ; 4 ; 38 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[13] ; 65 ; 4 ; 38 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[14] ; 69 ; 4 ; 43 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[15] ; 70 ; 4 ; 43 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[1] ; 76 ; 5 ; 50 ; 2 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[2] ; 77 ; 5 ; 50 ; 2 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[3] ; 79 ; 5 ; 50 ; 8 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[4] ; 81 ; 5 ; 50 ; 8 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[5] ; 84 ; 5 ; 50 ; 11 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[6] ; 105 ; 6 ; 50 ; 26 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[7] ; 102 ; 6 ; 50 ; 22 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[8] ; 57 ; 3 ; 21 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
+; sr_dq[9] ; 58 ; 3 ; 24 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; On ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; User ; 0 pF ; - ;
++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------------+----------------------+----------------------+---------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------+
+; Dual Purpose and Dedicated Pins ;
++----------+----------------------------------------------------+--------------------------------+------------------+------------------+
+; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
++----------+----------------------------------------------------+--------------------------------+------------------+------------------+
+; 15 ; JTAGEN ; Use as regular IO ; gpio_jtagen ; Dual Purpose Pin ;
+; 16 ; DIFFIO_RX_L11n, DIFFOUT_L11n, TMS, Low_Speed ; Reserved as secondary function ; ~ALTERA_TMS~ ; Dual Purpose Pin ;
+; 18 ; DIFFIO_RX_L11p, DIFFOUT_L11p, TCK, Low_Speed ; Reserved as secondary function ; ~ALTERA_TCK~ ; Dual Purpose Pin ;
+; 19 ; DIFFIO_RX_L12n, DIFFOUT_L12n, TDI, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDI~ ; Dual Purpose Pin ;
+; 20 ; DIFFIO_RX_L12p, DIFFOUT_L12p, TDO, Low_Speed ; Reserved as secondary function ; ~ALTERA_TDO~ ; Dual Purpose Pin ;
+; 121 ; DIFFIO_RX_T28n, DIFFOUT_T28n, DEV_CLRn, Low_Speed ; Use as regular IO ; abc_ad[0] ; Dual Purpose Pin ;
+; 122 ; DEV_OE ; Use as regular IO ; abc_xm_n ; Dual Purpose Pin ;
+; 126 ; CONFIG_SEL, Low_Speed ; Use as regular IO ; sr_a[5] ; Dual Purpose Pin ;
+; 134 ; DIFFIO_RX_T34n, DIFFOUT_T34n, CRC_ERROR, Low_Speed ; Use as regular IO ; abc_adsel[1] ; Dual Purpose Pin ;
+; 138 ; DIFFIO_RX_T36n, DIFFOUT_T36n, CONF_DONE, Low_Speed ; Use as regular IO ; tty_cts ; Dual Purpose Pin ;
++----------+----------------------------------------------------+--------------------------------+------------------+------------------+
+
+
++-------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+-------------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+-------------------+---------------+--------------+
+; 1A ; 8 / 8 ( 100 % ) ; 3.3V ; -- ;
+; 1B ; 9 / 10 ( 90 % ) ; 3.3V ; -- ;
+; 2 ; 7 / 7 ( 100 % ) ; 3.3V ; -- ;
+; 3 ; 18 / 18 ( 100 % ) ; 3.3V ; -- ;
+; 4 ; 7 / 7 ( 100 % ) ; 3.3V ; -- ;
+; 5 ; 12 / 12 ( 100 % ) ; 3.3V ; -- ;
+; 6 ; 15 / 15 ( 100 % ) ; 3.3V ; -- ;
+; 7 ; 6 / 7 ( 86 % ) ; 3.3V ; -- ;
+; 8 ; 15 / 17 ( 88 % ) ; 3.3V ; -- ;
++----------+-------------------+---------------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------+------------------------------------------------+--------+-----------------------+-----------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+------------------------------------------------+--------+-----------------------+-----------+------------+-----------------+----------+--------------+
+; 1 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 2 ; ; -- ; VCCA6 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 5 ; ; -- ; VCCA3 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 6 ; 0 ; 1A ; esp_int ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 7 ; 2 ; 1A ; gpio[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 8 ; 4 ; 1A ; gpio[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 9 ; ; 1A ; VCCIO1A ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 10 ; 6 ; 1A ; gpio[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 11 ; 8 ; 1A ; gpio[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 12 ; 10 ; 1A ; gpio[1] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 13 ; 12 ; 1A ; gpio[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 14 ; 14 ; 1A ; led[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 15 ; 18 ; 1B ; gpio_jtagen ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 16 ; 20 ; 1B ; ~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ;
+; 17 ; 21 ; 1B ; led[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 18 ; 22 ; 1B ; ~ALTERA_TCK~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ;
+; 19 ; 24 ; 1B ; ~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3 V Schmitt Trigger ; ; Row I/O ; N ; no ; On ;
+; 20 ; 26 ; 1B ; ~ALTERA_TDO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
+; 21 ; 28 ; 1B ; spi_miso ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 22 ; 30 ; 1B ; spi_mosi ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 23 ; ; 1B ; VCCIO1B ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 24 ; 32 ; 1B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
+; 25 ; 34 ; 1B ; spi_clk ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 26 ; 40 ; 2 ; clock_48 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 27 ; 42 ; 2 ; rtc_32khz ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 28 ; 44 ; 2 ; esp_io0 ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 29 ; 46 ; 2 ; spi_cs_esp_n ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 30 ; 49 ; 2 ; led[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 31 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 32 ; 64 ; 2 ; tty_rxd ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 33 ; 66 ; 2 ; sr_clk ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 34 ; ; -- ; VCCA2 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 35 ; ; -- ; VCCA1 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 36 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 37 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 38 ; 68 ; 3 ; sd_dat[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 39 ; 70 ; 3 ; sd_dat[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 40 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 41 ; 72 ; 3 ; sd_cmd ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 42 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 43 ; 74 ; 3 ; sr_a[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 44 ; 76 ; 3 ; sr_a[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 45 ; 78 ; 3 ; sr_a[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 46 ; 92 ; 3 ; sr_a[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 47 ; 94 ; 3 ; sr_a[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 48 ; 97 ; 3 ; sd_clk ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 49 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 50 ; 96 ; 3 ; sr_a[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 51 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 52 ; 98 ; 3 ; sr_cke ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 53 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 54 ; 100 ; 3 ; sd_dat[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 55 ; 104 ; 3 ; tty_txd ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 56 ; 106 ; 3 ; sr_dqm[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 57 ; 108 ; 3 ; sr_dq[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 58 ; 110 ; 3 ; sr_dq[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 59 ; 112 ; 3 ; sr_dq[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 60 ; 114 ; 3 ; sr_dq[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 61 ; 133 ; 4 ; i2c_scl ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 62 ; 134 ; 4 ; i2c_sda ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 63 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 64 ; 140 ; 4 ; sr_dq[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 65 ; 142 ; 4 ; sr_dq[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 66 ; 144 ; 4 ; sd_dat[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 67 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 68 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 69 ; 152 ; 4 ; sr_dq[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 70 ; 154 ; 4 ; sr_dq[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 71 ; ; -- ; VCCA5 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 72 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 73 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 74 ; 157 ; 5 ; sr_a[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 75 ; 156 ; 5 ; sr_dq[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 76 ; 159 ; 5 ; sr_dq[1] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 77 ; 158 ; 5 ; sr_dq[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 78 ; 177 ; 5 ; abc_nmi ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 79 ; 176 ; 5 ; sr_dq[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 80 ; 179 ; 5 ; abc_rdy_n ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 81 ; 178 ; 5 ; sr_dq[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 82 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 83 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 84 ; 185 ; 5 ; sr_dq[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 85 ; 184 ; 5 ; sr_a[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 86 ; 187 ; 5 ; sr_a[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 87 ; 186 ; 5 ; sr_a[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 88 ; 192 ; 6 ; abc_800 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 89 ; 194 ; 6 ; sr_a[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 90 ; 196 ; 6 ; abc_clk ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 91 ; 198 ; 6 ; sr_a[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 92 ; 200 ; 6 ; sr_ba[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 93 ; 202 ; 6 ; sr_ba[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 94 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 95 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 96 ; 216 ; 6 ; sr_cs_n ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 97 ; 217 ; 6 ; spi_cs_flash_n ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 98 ; 218 ; 6 ; sr_ras_n ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 99 ; 220 ; 6 ; sr_cas_n ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 100 ; 221 ; 6 ; sr_we_n ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 101 ; 222 ; 6 ; sr_dqm[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 102 ; 223 ; 6 ; sr_dq[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 103 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 104 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 105 ; 232 ; 6 ; sr_dq[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 106 ; 234 ; 6 ; tty_rts ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; On ;
+; 107 ; ; -- ; VCCA3 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 108 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 109 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 110 ; 236 ; 7 ; abc_ad[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 111 ; 238 ; 7 ; abc_ad[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 112 ; 255 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
+; 113 ; 258 ; 7 ; abc_ad[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 114 ; 260 ; 7 ; abc_ad[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 115 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 116 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 117 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 118 ; 280 ; 7 ; abc_ad[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 119 ; 282 ; 7 ; abc_ad[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 120 ; 292 ; 8 ; abc_ad[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 121 ; 294 ; 8 ; abc_ad[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 122 ; 296 ; 8 ; abc_xm_n ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 123 ; 299 ; 8 ; abc_memwr_n ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 124 ; 301 ; 8 ; abc_int_n ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 125 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 126 ; 300 ; 8 ; sr_a[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; On ;
+; 127 ; 303 ; 8 ; abc_resin ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 128 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 129 ; 302 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; 130 ; 304 ; 8 ; abc_iowr_n ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 131 ; 306 ; 8 ; abc_iord_n ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 132 ; 308 ; 8 ; abc_memrd_n ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 133 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 134 ; 310 ; 8 ; abc_adsel[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 135 ; 311 ; 8 ; abc_adsel[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 136 ; 312 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
+; 137 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 138 ; 314 ; 8 ; tty_cts ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 139 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 140 ; 316 ; 8 ; tty_dtr ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 141 ; 318 ; 8 ; rtc_int_n ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; On ;
+; 142 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; 143 ; ; -- ; VCCA4 ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
+; 144 ; ; -- ; VCC_ONE ; power ; ; 3.0V/3.3V ; -- ; ; -- ; -- ;
++----------+------------+----------+------------------------------------------------+--------+-----------------------+-----------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++------------------------------------------------------------------------------------------------+
+; PLL Summary ;
++-------------------------------+----------------------------------------------------------------+
+; Name ; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1 ;
++-------------------------------+----------------------------------------------------------------+
+; SDC pin name ; pll|altpll_component|auto_generated|pll1 ;
+; PLL mode ; Normal ;
+; Compensate clock ; clock0 ;
+; Compensated input/output pins ; -- ;
+; Switchover type ; -- ;
+; Input frequency 0 ; 48.0 MHz ;
+; Input frequency 1 ; -- ;
+; Nominal PFD frequency ; 48.0 MHz ;
+; Nominal VCO frequency ; 1152.0 MHz ;
+; VCO post scale K counter ; -- ;
+; VCO frequency control ; Manual Phase ;
+; VCO phase shift step ; 108 ps ;
+; VCO multiply ; -- ;
+; VCO divide ; -- ;
+; Freq min lock ; 25.01 MHz ;
+; Freq max lock ; 54.18 MHz ;
+; M VCO Tap ; 0 ;
+; M Initial ; 1 ;
+; M value ; 24 ;
+; N value ; 1 ;
+; Charge pump current ; setting 1 ;
+; Loop filter resistance ; setting 27 ;
+; Loop filter capacitance ; setting 0 ;
+; Bandwidth ; 680 kHz to 980 kHz ;
+; Bandwidth type ; Medium ;
+; Real time reconfigurable ; Off ;
+; Scan chain MIF file ; -- ;
+; Preserve PLL counter order ; Off ;
+; PLL location ; PLL_1 ;
+; Inclk0 signal ; clock_48 ;
+; Inclk1 signal ; -- ;
+; Inclk0 signal type ; Dedicated Pin ;
+; Inclk1 signal type ; -- ;
++-------------------------------+----------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; PLL Usage ;
++----------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------+
+; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ;
++----------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------+
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] ; clock0 ; 3 ; 1 ; 144.0 MHz ; 0 (0 ps) ; 5.62 (108 ps) ; 50/50 ; C0 ; 8 ; 4/4 Even ; -- ; 1 ; 0 ; pll|altpll_component|auto_generated|pll1|clk[0] ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] ; clock1 ; 2 ; 1 ; 96.0 MHz ; 0 (0 ps) ; 3.75 (108 ps) ; 50/50 ; C1 ; 12 ; 6/6 Even ; -- ; 1 ; 0 ; pll|altpll_component|auto_generated|pll1|clk[1] ;
++----------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------+
+
+
++----------------------------------------------+
+; I/O Assignment Warnings ;
++----------------+-----------------------------+
+; Pin Name ; Reason ;
++----------------+-----------------------------+
+; abc_adsel[0] ; Missing drive strength ;
+; abc_adsel[1] ; Missing drive strength ;
+; abc_rdy_n ; Missing drive strength ;
+; abc_resin ; Missing drive strength ;
+; abc_nmi ; Missing drive strength ;
+; abc_int_n ; Missing drive strength ;
+; abc_xm_n ; Missing drive strength ;
+; sr_cke ; Missing drive strength ;
+; sr_ba[0] ; Missing drive strength ;
+; sr_ba[1] ; Missing drive strength ;
+; sr_a[0] ; Missing drive strength ;
+; sr_a[1] ; Missing drive strength ;
+; sr_a[2] ; Missing drive strength ;
+; sr_a[3] ; Missing drive strength ;
+; sr_a[4] ; Missing drive strength ;
+; sr_a[5] ; Missing drive strength ;
+; sr_a[6] ; Missing drive strength ;
+; sr_a[7] ; Missing drive strength ;
+; sr_a[8] ; Missing drive strength ;
+; sr_a[9] ; Missing drive strength ;
+; sr_a[10] ; Missing drive strength ;
+; sr_a[11] ; Missing drive strength ;
+; sr_a[12] ; Missing drive strength ;
+; sr_dqm[0] ; Missing drive strength ;
+; sr_dqm[1] ; Missing drive strength ;
+; sr_cs_n ; Missing drive strength ;
+; sr_we_n ; Missing drive strength ;
+; sr_cas_n ; Missing drive strength ;
+; sr_ras_n ; Missing drive strength ;
+; sd_clk ; Missing drive strength ;
+; sd_cmd ; Missing drive strength ;
+; tty_rxd ; Missing drive strength ;
+; tty_cts ; Missing drive strength ;
+; led[1] ; Missing drive strength ;
+; led[2] ; Missing drive strength ;
+; led[3] ; Missing drive strength ;
+; abc_ad[0] ; Missing drive strength ;
+; abc_ad[1] ; Missing drive strength ;
+; abc_ad[2] ; Missing drive strength ;
+; abc_ad[3] ; Missing drive strength ;
+; abc_ad[4] ; Missing drive strength ;
+; abc_ad[5] ; Missing drive strength ;
+; abc_ad[6] ; Missing drive strength ;
+; abc_ad[7] ; Missing drive strength ;
+; sr_dq[0] ; Missing drive strength ;
+; sr_dq[1] ; Missing drive strength ;
+; sr_dq[2] ; Missing drive strength ;
+; sr_dq[3] ; Missing drive strength ;
+; sr_dq[4] ; Missing drive strength ;
+; sr_dq[5] ; Missing drive strength ;
+; sr_dq[6] ; Missing drive strength ;
+; sr_dq[7] ; Missing drive strength ;
+; sr_dq[8] ; Missing drive strength ;
+; sr_dq[9] ; Missing drive strength ;
+; sr_dq[10] ; Missing drive strength ;
+; sr_dq[11] ; Missing drive strength ;
+; sr_dq[12] ; Missing drive strength ;
+; sr_dq[13] ; Missing drive strength ;
+; sr_dq[14] ; Missing drive strength ;
+; sr_dq[15] ; Missing drive strength ;
+; sd_dat[0] ; Missing drive strength ;
+; sd_dat[1] ; Missing drive strength ;
+; sd_dat[2] ; Missing drive strength ;
+; sd_dat[3] ; Missing drive strength ;
+; spi_clk ; Missing drive strength ;
+; spi_miso ; Missing drive strength ;
+; spi_mosi ; Missing drive strength ;
+; spi_cs_esp_n ; Missing drive strength ;
+; spi_cs_flash_n ; Missing drive strength ;
+; esp_io0 ; Missing drive strength ;
+; esp_int ; Missing drive strength ;
+; i2c_scl ; Missing drive strength ;
+; i2c_sda ; Missing drive strength ;
+; gpio[0] ; Missing drive strength ;
+; gpio[1] ; Missing drive strength ;
+; gpio[2] ; Missing drive strength ;
+; gpio[3] ; Missing drive strength ;
+; gpio[4] ; Missing drive strength ;
+; gpio[5] ; Missing drive strength ;
+; gpio_jtagen ; Missing drive strength ;
+; sr_a[5] ; Missing location assignment ;
++----------------+-----------------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+-----------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ;
++--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+-----------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
+; |max80 ; 20 (15) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 93 ; 0 ; 7 (2) ; 0 (0) ; 13 (13) ; 0 ; |max80 ; max80 ; work ;
+; |pll:pll| ; 5 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 0 (0) ; 0 ; |max80|pll:pll ; pll ; work ;
+; |altpll:altpll_component| ; 5 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 0 (0) ; 0 ; |max80|pll:pll|altpll:altpll_component ; altpll ; work ;
+; |pll_altpll:auto_generated| ; 5 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (3) ; 0 (0) ; 0 (0) ; 0 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated ; pll_altpll ; work ;
+; |pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le12:altpll_dyn_phase_le5 ; pll_altpll_dyn_phase_le12 ; work ;
+; |pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le1:altpll_dyn_phase_le4 ; pll_altpll_dyn_phase_le1 ; work ;
+; |pll_altpll_dyn_phase_le:altpll_dyn_phase_le2| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; |max80|pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll_altpll_dyn_phase_le:altpll_dyn_phase_le2 ; pll_altpll_dyn_phase_le ; work ;
++--------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+------------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+------------+-----------------------------------------------------------------------------------------------------------------+---------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++----------------+----------+---------------+---------------+-----------------------+-----+------+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
++----------------+----------+---------------+---------------+-----------------------+-----+------+
+; abc_clk ; Input ; -- ; -- ; -- ; -- ; -- ;
+; abc_adsel[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; abc_adsel[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; abc_memwr_n ; Input ; -- ; -- ; -- ; -- ; -- ;
+; abc_memrd_n ; Input ; -- ; -- ; -- ; -- ; -- ;
+; abc_iowr_n ; Input ; -- ; -- ; -- ; -- ; -- ;
+; abc_iord_n ; Input ; -- ; -- ; -- ; -- ; -- ;
+; abc_rdy_n ; Output ; -- ; -- ; -- ; -- ; -- ;
+; abc_resin ; Output ; -- ; -- ; -- ; -- ; -- ;
+; abc_nmi ; Output ; -- ; -- ; -- ; -- ; -- ;
+; abc_int_n ; Output ; -- ; -- ; -- ; -- ; -- ;
+; abc_xm_n ; Output ; -- ; -- ; -- ; -- ; -- ;
+; abc_800 ; Input ; -- ; -- ; -- ; -- ; -- ;
+; sr_clk ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_cke ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_ba[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_ba[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_a[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_a[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_a[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_a[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_a[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_a[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_a[6] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_a[7] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_a[8] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_a[9] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_a[10] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_a[11] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_a[12] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_dqm[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_dqm[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_cs_n ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_we_n ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_cas_n ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sr_ras_n ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sd_clk ; Output ; -- ; -- ; -- ; -- ; -- ;
+; sd_cmd ; Output ; -- ; -- ; -- ; -- ; -- ;
+; tty_txd ; Input ; -- ; -- ; -- ; -- ; -- ;
+; tty_rxd ; Output ; -- ; -- ; -- ; -- ; -- ;
+; tty_rts ; Input ; -- ; -- ; -- ; -- ; -- ;
+; tty_cts ; Output ; -- ; -- ; -- ; -- ; -- ;
+; tty_dtr ; Input ; -- ; -- ; -- ; -- ; -- ;
+; rtc_32khz ; Input ; -- ; -- ; -- ; -- ; -- ;
+; rtc_int_n ; Input ; -- ; -- ; -- ; -- ; -- ;
+; led[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; led[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; led[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
+; abc_ad[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; abc_ad[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; abc_ad[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; abc_ad[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; abc_ad[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; abc_ad[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; abc_ad[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; abc_ad[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[8] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[9] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[10] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[11] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[12] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[13] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[14] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sr_dq[15] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sd_dat[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sd_dat[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sd_dat[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; sd_dat[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; spi_clk ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; spi_miso ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; spi_mosi ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; spi_cs_esp_n ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; spi_cs_flash_n ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; esp_io0 ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; esp_int ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; i2c_scl ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; i2c_sda ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; gpio[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; gpio[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; gpio[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; gpio[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; gpio[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; gpio[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; gpio_jtagen ; Bidir ; -- ; -- ; -- ; -- ; -- ;
+; clock_48 ; Input ; -- ; -- ; -- ; -- ; -- ;
++----------------+----------+---------------+---------------+-----------------------+-----+------+
+
+
++---------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++---------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------+-------------------+---------+
+; abc_clk ; ; ;
+; abc_memwr_n ; ; ;
+; abc_memrd_n ; ; ;
+; abc_iowr_n ; ; ;
+; abc_iord_n ; ; ;
+; abc_800 ; ; ;
+; tty_txd ; ; ;
+; tty_rts ; ; ;
+; tty_dtr ; ; ;
+; rtc_32khz ; ; ;
+; rtc_int_n ; ; ;
+; abc_ad[0] ; ; ;
+; abc_ad[1] ; ; ;
+; abc_ad[2] ; ; ;
+; abc_ad[3] ; ; ;
+; abc_ad[4] ; ; ;
+; abc_ad[5] ; ; ;
+; abc_ad[6] ; ; ;
+; abc_ad[7] ; ; ;
+; sr_dq[0] ; ; ;
+; sr_dq[1] ; ; ;
+; sr_dq[2] ; ; ;
+; sr_dq[3] ; ; ;
+; sr_dq[4] ; ; ;
+; sr_dq[5] ; ; ;
+; sr_dq[6] ; ; ;
+; sr_dq[7] ; ; ;
+; sr_dq[8] ; ; ;
+; sr_dq[9] ; ; ;
+; sr_dq[10] ; ; ;
+; sr_dq[11] ; ; ;
+; sr_dq[12] ; ; ;
+; sr_dq[13] ; ; ;
+; sr_dq[14] ; ; ;
+; sr_dq[15] ; ; ;
+; sd_dat[0] ; ; ;
+; sd_dat[1] ; ; ;
+; sd_dat[2] ; ; ;
+; sd_dat[3] ; ; ;
+; spi_clk ; ; ;
+; spi_miso ; ; ;
+; spi_mosi ; ; ;
+; spi_cs_esp_n ; ; ;
+; spi_cs_flash_n ; ; ;
+; esp_io0 ; ; ;
+; esp_int ; ; ;
+; i2c_scl ; ; ;
+; i2c_sda ; ; ;
+; gpio[0] ; ; ;
+; gpio[1] ; ; ;
+; gpio[2] ; ; ;
+; gpio[3] ; ; ;
+; gpio[4] ; ; ;
+; gpio[5] ; ; ;
+; gpio_jtagen ; ; ;
+; clock_48 ; ; ;
++---------------------+-------------------+---------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++----------------------------------------------------------------------------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------------------------------------------------------------------------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
+; clock_48 ; PIN_26 ; 1 ; Clock ; no ; -- ; -- ; -- ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] ; PLL_1 ; 13 ; Clock ; yes ; Global Clock ; GCLK19 ; -- ;
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_locked ; PLL_1 ; 13 ; Async. clear ; no ; -- ; -- ; -- ;
++----------------------------------------------------------------------------+----------+---------+--------------+--------+----------------------+------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals ;
++----------------------------------------------------------------------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------------------------------------------------------------------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+; pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] ; PLL_1 ; 13 ; 0 ; Global Clock ; GCLK19 ; -- ;
++----------------------------------------------------------------------------+----------+---------+--------------------------------------+----------------------+------------------+---------------------------+
+
+
++-----------------------------------------------+
+; Routing Usage Summary ;
++-----------------------+-----------------------+
+; Routing Resource Type ; Usage ;
++-----------------------+-----------------------+
+; Block interconnects ; 9 / 49,625 ( < 1 % ) ;
+; C16 interconnects ; 0 / 2,250 ( 0 % ) ;
+; C4 interconnects ; 7 / 39,600 ( < 1 % ) ;
+; Direct links ; 5 / 49,625 ( < 1 % ) ;
+; Global clocks ; 1 / 20 ( 5 % ) ;
+; Local interconnects ; 16 / 15,840 ( < 1 % ) ;
+; NSLEEPs ; 0 / 320 ( 0 % ) ;
+; R24 interconnects ; 0 / 2,146 ( 0 % ) ;
+; R4 interconnects ; 4 / 53,244 ( < 1 % ) ;
++-----------------------+-----------------------+
+
+
++--------------------------------------------------------------------------+
+; LAB Logic Elements ;
++--------------------------------------------+-----------------------------+
+; Number of Logic Elements (Average = 7.00) ; Number of LABs (Total = 3) ;
++--------------------------------------------+-----------------------------+
+; 1 ; 1 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 1 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 1 ;
+; 14 ; 0 ;
+; 15 ; 0 ;
+; 16 ; 0 ;
++--------------------------------------------+-----------------------------+
+
+
++------------------------------------------------------------------+
+; LAB-wide Signals ;
++------------------------------------+-----------------------------+
+; LAB-wide Signals (Average = 0.67) ; Number of LABs (Total = 3) ;
++------------------------------------+-----------------------------+
+; 1 Async. clear ; 1 ;
+; 1 Clock ; 1 ;
++------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced (Average = 11.33) ; Number of LABs (Total = 3) ;
++----------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 1 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 1 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 0 ;
+; 15 ; 0 ;
+; 16 ; 0 ;
+; 17 ; 0 ;
+; 18 ; 0 ;
+; 19 ; 0 ;
+; 20 ; 0 ;
+; 21 ; 0 ;
+; 22 ; 0 ;
+; 23 ; 0 ;
+; 24 ; 0 ;
+; 25 ; 0 ;
+; 26 ; 1 ;
++----------------------------------------------+-----------------------------+
+
+
++-------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++-------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out (Average = 1.67) ; Number of LABs (Total = 3) ;
++-------------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 2 ;
+; 2 ; 0 ;
+; 3 ; 1 ;
++-------------------------------------------------+-----------------------------+
+
+
++---------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++---------------------------------------------+-----------------------------+
+; Number of Distinct Inputs (Average = 0.67) ; Number of LABs (Total = 3) ;
++---------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 1 ;
++---------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary ;
++----------------------------------+-------+
+; I/O Rules Statistic ; Total ;
++----------------------------------+-------+
+; Total I/O Rules ; 30 ;
+; Number of I/O Rules Passed ; 14 ;
+; Number of I/O Rules Failed ; 0 ;
+; Number of I/O Rules Unchecked ; 0 ;
+; Number of I/O Rules Inapplicable ; 16 ;
++----------------------------------+-------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------+--------+------+-------------------+
+; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Device ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------+--------+------+-------------------+
+; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; ALL ; I/O ; ;
+; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
+; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; ALL ; I/O ; ;
+; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
+; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; ALL ; I/O ; ;
+; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
+; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; ALL ; I/O ; ;
+; Pass ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
+; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; ALL ; I/O ; ;
+; Pass ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; ALL ; I/O ; ;
+; Pass ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
+; Pass ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Termination assignments found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; ALL ; I/O ; ;
+; Pass ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
+; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; ALL ; I/O ; ;
+; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 160mA for row I/Os and 160mA for column I/Os. ; Critical ; 0 such failures found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; ALL ; I/O ; ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; ALL ; I/O ; ;
++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+-------------------------------------------------+--------+------+-------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Pin/Rules ; IO_000002 ; IO_000003 ; IO_000001 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000010 ; IO_000009 ; IO_000046 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000045 ; IO_000019 ; IO_000018 ; IO_000022 ; IO_000021 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000011 ; IO_000020 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+; Total Pass ; 0 ; 92 ; 92 ; 0 ; 0 ; 93 ; 92 ; 0 ; 93 ; 93 ; 0 ; 0 ; 0 ; 93 ; 56 ; 0 ; 0 ; 1 ; 0 ; 93 ; 44 ; 0 ; 0 ; 0 ; 1 ; 56 ; 0 ; 93 ; 0 ; 0 ;
+; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Inapplicable ; 93 ; 1 ; 1 ; 93 ; 93 ; 0 ; 1 ; 93 ; 0 ; 0 ; 93 ; 93 ; 93 ; 0 ; 37 ; 93 ; 93 ; 92 ; 93 ; 0 ; 49 ; 93 ; 93 ; 93 ; 92 ; 37 ; 93 ; 0 ; 93 ; 93 ;
+; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; abc_clk ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_adsel[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_adsel[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_memwr_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_memrd_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_iowr_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_iord_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_rdy_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_resin ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_nmi ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_int_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_xm_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_800 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_clk ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_cke ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_ba[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_ba[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_a[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_a[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_a[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_a[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_a[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_a[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_a[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_a[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_a[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_a[9] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_a[10] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_a[11] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_a[12] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dqm[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dqm[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_cs_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_we_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_cas_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_ras_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sd_clk ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sd_cmd ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; tty_txd ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; tty_rxd ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; tty_rts ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; tty_cts ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; tty_dtr ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; rtc_32khz ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; rtc_int_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; led[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; led[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; led[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_ad[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_ad[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_ad[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_ad[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_ad[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_ad[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_ad[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; abc_ad[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[8] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[9] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[10] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[11] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[12] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[13] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[14] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sr_dq[15] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sd_dat[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sd_dat[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sd_dat[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; sd_dat[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; spi_clk ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; spi_miso ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; spi_mosi ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; spi_cs_esp_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; spi_cs_flash_n ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; esp_io0 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; esp_int ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; i2c_scl ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; i2c_sda ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; gpio[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; gpio[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; gpio[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; gpio[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; gpio[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; gpio[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; gpio_jtagen ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
+; clock_48 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
+
+
++-------------------------------------------------------------------------------------------+
+; Fitter Device Options ;
++------------------------------------------------------------------+------------------------+
+; Option ; Setting ;
++------------------------------------------------------------------+------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Internal Configuration ;
+; Enable Error Detection CRC_ERROR pin ; Off ;
+; Enable open drain on CRC_ERROR pin ; Off ;
+; Enable nCONFIG, nSTATUS, and CONF_DONE pins ; Off ;
+; Enable JTAG pin sharing ; Off ;
+; Enable nCE pin ; Off ;
+; Enable CONFIG_SEL pin ; Off ;
+; Enable input tri-state on active configuration pins in user mode ; Off ;
+; Configuration Voltage Level ; Auto ;
+; Force Configuration Voltage Level ; Off ;
+; Data[0] ; Unreserved ;
+; Data[1]/ASDO ; Unreserved ;
+; FLASH_nCE/nCSO ; Unreserved ;
+; DCLK ; Unreserved ;
++------------------------------------------------------------------+------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.20 V ;
+; Low Junction Temperature ; 0 C ;
+; High Junction Temperature ; 85 C ;
++---------------------------+--------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
+Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
+Info (119006): Selected device 10M16SCE144C8G for design "max80"
+Info (119018): Selected Migration Device List
+ Info (119019): Selected 10M04SCE144C8G for migration
+ Info (119019): Selected 10M08SCE144C8G for migration
+ Info (119019): Selected 10M25SCE144C8G for migration
+Info (119021): Selected migration device list is legal with 101 total of migratable pins
+Info (21077): Low junction temperature is 0 degrees C
+Info (21077): High junction temperature is 85 degrees C
+Warning (15536): Implemented PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" as MAX 10 PLL type, but with warnings File: /home/hpa/abc80/max80/fpga-template/db/pll_altpll.v Line: 491
+ Info (15552): PLL constraints from migration devices are also being used File: /home/hpa/abc80/max80/fpga-template/db/pll_altpll.v Line: 491
+ Warning (15520): Can't achieve requested value 1 ps of parameter vco_phase_shift_step -- achieved value of 108 ps File: /home/hpa/abc80/max80/fpga-template/db/pll_altpll.v Line: 491
+ Info (15099): Implementing clock multiplication of 3, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] port File: /home/hpa/abc80/max80/fpga-template/db/pll_altpll.v Line: 491
+ Info (15099): Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] port File: /home/hpa/abc80/max80/fpga-template/db/pll_altpll.v Line: 491
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Critical Warning (16562): Review the Power Analyzer report file (<design>.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures.
+Info (165059): Selected device migration path cannot use 2 pins as DQS I/Os
+ Info (165060): Pin 85
+ Info (165060): Pin 96
+Info (165059): Selected device migration path cannot use 2 pins as nDQS I/Os
+ Info (165060): Pin 87
+ Info (165060): Pin 98
+Info (165059): Selected device migration path cannot use 10 pins as DQ I/Os
+ Info (165060): Pin 85
+ Info (165060): Pin 84
+ Info (165060): Pin 87
+ Info (165060): Pin 86
+ Info (165060): Pin 96
+ Info (165060): Pin 98
+ Info (165060): Pin 99
+ Info (165060): Pin 100
+ Info (165060): Pin 101
+ Info (165060): Pin 102
+Info (165059): Selected device migration path cannot use 4 pins as PLL External Output Clock I/Os
+ Info (165060): Pin 69
+ Info (165060): Pin 70
+ Info (165060): Pin 140
+ Info (165060): Pin 141
+Info (165059): Selected device migration path cannot use 1 pins as RUP I/Os
+ Info (165060): Pin 75
+Info (165059): Selected device migration path cannot use 1 pins as RDN I/Os
+ Info (165060): Pin 77
+Info (169124): Fitter converted 4 user pins into dedicated programming pins
+ Info (169125): Pin ~ALTERA_TMS~ is reserved at location 16
+ Info (169125): Pin ~ALTERA_TCK~ is reserved at location 18
+ Info (169125): Pin ~ALTERA_TDI~ is reserved at location 19
+ Info (169125): Pin ~ALTERA_TDO~ is reserved at location 20
+Info (169141): DATA[0] dual-purpose pin not reserved
+Info (12825): Data[1]/ASDO dual-purpose pin not reserved
+Info (12825): nCSO dual-purpose pin not reserved
+Info (12825): DCLK dual-purpose pin not reserved
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 93 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
+Critical Warning (176584): Output pin "sr_clk" (external output clock of PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1") uses I/O standard 3.3-V LVTTL, has current strength 8mA, output load 0pF, and output clock frequency of 144 MHz, but target device can support only maximum output clock frequency of 125 MHz for this combination of I/O standard, current strength and load File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 112
+Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] (placed in counter C0 of PLL_1) File: /home/hpa/abc80/max80/fpga-template/db/pll_altpll.v Line: 605
+ Info (176355): Automatically promoted destinations to use location or clock signal External Clock Output CLKCTRL_PLL1E0
+Info (176353): Automatically promoted node pll:pll|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[1] (placed in counter C1 of PLL_1) File: /home/hpa/abc80/max80/fpga-template/db/pll_altpll.v Line: 605
+ Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19
+Info (332164): Evaluating HDL-embedded SDC commands
+ Info (332165): Entity pll_altpll
+ Info (332166): set_false_path -from ** -to *phasedone_state*
+ Info (332166): set_false_path -from ** -to *internal_phasestep*
+Warning (332174): Ignored filter at qfit2_legacy_fmain_fitter_flow.tcl(117): *phasedone_state* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
+Warning (332049): Ignored set_false_path at qfit2_legacy_fmain_fitter_flow.tcl(117): Argument <to> is not an object ID File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
+ Info (332050): run_legacy_fitter_flow File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
+Warning (332174): Ignored filter at qfit2_legacy_fmain_fitter_flow.tcl(117): *internal_phasestep* could not be matched with a clock or keeper or register or port or pin or cell or partition File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
+Warning (332049): Ignored set_false_path at qfit2_legacy_fmain_fitter_flow.tcl(117): Argument <to> is not an object ID File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
+ Info (332050): run_legacy_fitter_flow File: /opt/altera/18.1/quartus/common/tcl/internal/qfit2_legacy_fmain_fitter_flow.tcl Line: 117
+Info (332104): Reading SDC File: 'max80.sdc'
+Info (332110): Deriving PLL clocks
+ Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[0]} {pll|altpll_component|auto_generated|pll1|clk[0]}
+ Info (332110): create_generated_clock -source {pll|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {pll|altpll_component|auto_generated|pll1|clk[1]} {pll|altpll_component|auto_generated|pll1|clk[1]}
+Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
+Warning (332174): Ignored filter at max80.sdc(29): *|synchronizer:*|qreg0* could not be matched with a register File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 29
+Warning (332049): Ignored set_multicycle_path at max80.sdc(30): Argument <to> is an empty collection File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 30
+ Info (332050): set_multicycle_path -from [all_clocks] -to $synchro_inputs \
+ -start -setup 2 File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 30
+Warning (332049): Ignored set_multicycle_path at max80.sdc(32): Argument <to> is an empty collection File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 32
+ Info (332050): set_multicycle_path -from [all_clocks] -to $synchro_inputs \
+ -start -hold -1 File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 32
+Warning (332174): Ignored filter at max80.sdc(36): sld_signaltap:* could not be matched with a register File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 36
+Warning (332049): Ignored set_false_path at max80.sdc(36): Argument <to> is an empty collection File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 36
+ Info (332050): set_false_path -to [get_registers sld_signaltap:*] File: /home/hpa/abc80/max80/fpga-template/max80.sdc Line: 36
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
+Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
+Info (332111): Found 5 clocks
+ Info (332111): Period Clock Name
+ Info (332111): ======== ============
+ Info (332111): 20.833 clock_48
+ Info (332111): 6.944 pll|altpll_component|auto_generated|pll1|clk[0]
+ Info (332111): 10.416 pll|altpll_component|auto_generated|pll1|clk[1]
+ Info (332111): 10.416 rst_n
+ Info (332111): 30517.000 rtc_32khz
+Info (176233): Starting register packing
+Info (176221): The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os.
+Info (176235): Finished register packing
+ Extra Info (176219): No registers were packed into other blocks
+Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+ Info (176211): Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
+ Info (176212): I/O standards used: 3.3-V LVTTL.
+Info (176215): I/O bank details before I/O pin placement
+ Info (176214): Statistics of I/O banks
+ Info (176213): I/O bank number 1A does not use VREF pins and has 3.3V VCCIO pins. 8 total pin(s) used -- 0 pins available
+ Info (176213): I/O bank number 1B does not use VREF pins and has 3.3V VCCIO pins. 9 total pin(s) used -- 1 pins available
+ Info (176213): I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 7 total pin(s) used -- 0 pins available
+ Info (176213): I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 18 total pin(s) used -- 0 pins available
+ Info (176213): I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 7 total pin(s) used -- 0 pins available
+ Info (176213): I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 12 total pin(s) used -- 0 pins available
+ Info (176213): I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 15 total pin(s) used -- 0 pins available
+ Info (176213): I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 6 total pin(s) used -- 1 pins available
+ Info (176213): I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 14 total pin(s) used -- 3 pins available
+Warning (15058): PLL "pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins File: /home/hpa/abc80/max80/fpga-template/db/pll_altpll.v Line: 491
+Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
+Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 0% of the available device resources
+ Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X11_Y9
+Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info (170201): Optimizations that may affect the design's routability were skipped
+ Info (170200): Optimizations that may affect the design's timing were skipped
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
+Info (11888): Total time spent on timing analysis during the Fitter is 0.04 seconds.
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Info (334004): Delay annotation completed successfully
+Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
+Warning (169177): 56 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
+ Info (169178): Pin abc_clk uses I/O standard 3.3-V LVTTL at 90 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 14
+ Info (169178): Pin abc_memwr_n uses I/O standard 3.3-V LVTTL at 123 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 17
+ Info (169178): Pin abc_memrd_n uses I/O standard 3.3-V LVTTL at 132 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 18
+ Info (169178): Pin abc_iowr_n uses I/O standard 3.3-V LVTTL at 130 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 19
+ Info (169178): Pin abc_iord_n uses I/O standard 3.3-V LVTTL at 131 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 20
+ Info (169178): Pin abc_800 uses I/O standard 3.3-V LVTTL at 88 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 26
+ Info (169178): Pin tty_txd uses I/O standard 3.3-V LVTTL at 55 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 46
+ Info (169178): Pin tty_rts uses I/O standard 3.3-V LVTTL at 106 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 48
+ Info (169178): Pin tty_dtr uses I/O standard 3.3-V LVTTL at 140 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 50
+ Info (169178): Pin rtc_32khz uses I/O standard 3.3-V LVTTL at 27 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 66
+ Info (169178): Pin rtc_int_n uses I/O standard 3.3-V LVTTL at 141 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 67
+ Info (169178): Pin abc_ad[0] uses I/O standard 3.3-V LVTTL at 121 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169178): Pin abc_ad[1] uses I/O standard 3.3-V LVTTL at 120 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169178): Pin abc_ad[2] uses I/O standard 3.3-V LVTTL at 119 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169178): Pin abc_ad[3] uses I/O standard 3.3-V LVTTL at 118 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169178): Pin abc_ad[4] uses I/O standard 3.3-V LVTTL at 114 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169178): Pin abc_ad[5] uses I/O standard 3.3-V LVTTL at 113 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169178): Pin abc_ad[6] uses I/O standard 3.3-V LVTTL at 111 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169178): Pin abc_ad[7] uses I/O standard 3.3-V LVTTL at 110 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169178): Pin sr_dq[0] uses I/O standard 3.3-V LVTTL at 75 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[1] uses I/O standard 3.3-V LVTTL at 76 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[2] uses I/O standard 3.3-V LVTTL at 77 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[3] uses I/O standard 3.3-V LVTTL at 79 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[4] uses I/O standard 3.3-V LVTTL at 81 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[5] uses I/O standard 3.3-V LVTTL at 84 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[6] uses I/O standard 3.3-V LVTTL at 105 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[7] uses I/O standard 3.3-V LVTTL at 102 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[8] uses I/O standard 3.3-V LVTTL at 57 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[9] uses I/O standard 3.3-V LVTTL at 58 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[10] uses I/O standard 3.3-V LVTTL at 59 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[11] uses I/O standard 3.3-V LVTTL at 60 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[12] uses I/O standard 3.3-V LVTTL at 64 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[13] uses I/O standard 3.3-V LVTTL at 65 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[14] uses I/O standard 3.3-V LVTTL at 69 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sr_dq[15] uses I/O standard 3.3-V LVTTL at 70 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169178): Pin sd_dat[0] uses I/O standard 3.3-V LVTTL at 54 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 43
+ Info (169178): Pin sd_dat[1] uses I/O standard 3.3-V LVTTL at 66 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 43
+ Info (169178): Pin sd_dat[2] uses I/O standard 3.3-V LVTTL at 38 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 43
+ Info (169178): Pin sd_dat[3] uses I/O standard 3.3-V LVTTL at 39 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 43
+ Info (169178): Pin spi_clk uses I/O standard 3.3-V LVTTL at 25 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 53
+ Info (169178): Pin spi_miso uses I/O standard 3.3-V LVTTL at 21 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 54
+ Info (169178): Pin spi_mosi uses I/O standard 3.3-V LVTTL at 22 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 55
+ Info (169178): Pin spi_cs_esp_n uses I/O standard 3.3-V LVTTL at 29 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 56
+ Info (169178): Pin spi_cs_flash_n uses I/O standard 3.3-V LVTTL at 97 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 57
+ Info (169178): Pin esp_io0 uses I/O standard 3.3-V LVTTL at 28 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 60
+ Info (169178): Pin esp_int uses I/O standard 3.3-V LVTTL at 6 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 61
+ Info (169178): Pin i2c_scl uses I/O standard 3.3-V LVTTL at 61 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 64
+ Info (169178): Pin i2c_sda uses I/O standard 3.3-V LVTTL at 62 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 65
+ Info (169178): Pin gpio[0] uses I/O standard 3.3-V LVTTL at 13 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 73
+ Info (169178): Pin gpio[1] uses I/O standard 3.3-V LVTTL at 12 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 73
+ Info (169178): Pin gpio[2] uses I/O standard 3.3-V LVTTL at 11 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 73
+ Info (169178): Pin gpio[3] uses I/O standard 3.3-V LVTTL at 10 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 73
+ Info (169178): Pin gpio[4] uses I/O standard 3.3-V LVTTL at 8 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 73
+ Info (169178): Pin gpio[5] uses I/O standard 3.3-V LVTTL at 7 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 73
+ Info (169178): Pin gpio_jtagen uses I/O standard 3.3-V LVTTL at 15 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 85
+ Info (169178): Pin clock_48 uses I/O standard 3.3-V LVTTL at 26 File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 11
+Warning (169064): Following 44 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
+ Info (169065): Pin abc_ad[0] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169065): Pin abc_ad[1] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169065): Pin abc_ad[2] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169065): Pin abc_ad[3] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169065): Pin abc_ad[4] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169065): Pin abc_ad[5] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169065): Pin abc_ad[6] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169065): Pin abc_ad[7] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 16
+ Info (169065): Pin sr_dq[0] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[1] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[2] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[3] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[4] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[5] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[6] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[7] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[8] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[9] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[10] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[11] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[12] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[13] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[14] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sr_dq[15] has a permanently enabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 33
+ Info (169065): Pin sd_dat[0] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 43
+ Info (169065): Pin sd_dat[1] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 43
+ Info (169065): Pin sd_dat[2] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 43
+ Info (169065): Pin sd_dat[3] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 43
+ Info (169065): Pin spi_clk has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 53
+ Info (169065): Pin spi_miso has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 54
+ Info (169065): Pin spi_mosi has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 55
+ Info (169065): Pin spi_cs_esp_n has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 56
+ Info (169065): Pin spi_cs_flash_n has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 57
+ Info (169065): Pin esp_io0 has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 60
+ Info (169065): Pin esp_int has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 61
+ Info (169065): Pin i2c_scl has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 64
+ Info (169065): Pin i2c_sda has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 65
+ Info (169065): Pin gpio[0] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 73
+ Info (169065): Pin gpio[1] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 73
+ Info (169065): Pin gpio[2] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 73
+ Info (169065): Pin gpio[3] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 73
+ Info (169065): Pin gpio[4] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 73
+ Info (169065): Pin gpio[5] has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 73
+ Info (169065): Pin gpio_jtagen has a permanently disabled output enable File: /home/hpa/abc80/max80/fpga-template/max80.sv Line: 85
+Info (144001): Generated suppressed messages file /home/hpa/abc80/max80/fpga-template/output_files/max80.fit.smsg
+Info: Quartus Prime Fitter was successful. 0 errors, 20 warnings
+ Info: Peak virtual memory: 1403 megabytes
+ Info: Processing ended: Mon Feb 22 15:40:17 2021
+ Info: Elapsed time: 00:00:08
+ Info: Total CPU time (on all processors): 00:00:08
+
+
++----------------------------+
+; Fitter Suppressed Messages ;
++----------------------------+
+The suppressed messages can be found in /home/hpa/abc80/max80/fpga-template/output_files/max80.fit.smsg.
+
+
diff --git a/output_files/max80.pin b/output_files/max80.pin
new file mode 100644
index 0000000..5fdb368
--- /dev/null
+++ b/output_files/max80.pin
@@ -0,0 +1,216 @@
+ -- Copyright (C) 2019 Intel Corporation. All rights reserved.
+ -- Your use of Intel Corporation's design tools, logic functions
+ -- and other software and tools, and any partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Intel Program License
+ -- Subscription Agreement, the Intel Quartus Prime License Agreement,
+ -- the Intel FPGA IP License Agreement, or other applicable license
+ -- agreement, including, without limitation, that your use is for
+ -- the sole purpose of programming logic devices manufactured by
+ -- Intel and sold by Intel or its authorized distributors. Please
+ -- refer to the applicable agreement for further details, at
+ -- https://fpgasoftware.intel.com/eula.
+ --
+ -- This is a Quartus Prime output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus Prime input file. This file cannot be used
+ -- to make Quartus Prime pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus Prime help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1A: 3.3V
+ -- Bank 1B: 3.3V
+ -- Bank 2: 3.3V
+ -- Bank 3: 3.3V
+ -- Bank 4: 3.3V
+ -- Bank 5: 3.3V
+ -- Bank 6: 3.3V
+ -- Bank 7: 3.3V
+ -- Bank 8: 3.3V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+CHIP "max80" ASSIGNED TO AN: 10M16SCE144C8G
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+VCC_ONE : 1 : power : : 3.0V/3.3V : :
+VCCA6 : 2 : power : : 3.0V/3.3V : :
+GND : 3 : gnd : : : :
+GND : 4 : gnd : : : :
+VCCA3 : 5 : power : : 3.0V/3.3V : :
+esp_int : 6 : bidir : 3.3-V LVTTL : : 1A : Y
+gpio[5] : 7 : bidir : 3.3-V LVTTL : : 1A : Y
+gpio[4] : 8 : bidir : 3.3-V LVTTL : : 1A : Y
+VCCIO1A : 9 : power : : 3.3V : 1A :
+gpio[3] : 10 : bidir : 3.3-V LVTTL : : 1A : Y
+gpio[2] : 11 : bidir : 3.3-V LVTTL : : 1A : Y
+gpio[1] : 12 : bidir : 3.3-V LVTTL : : 1A : Y
+gpio[0] : 13 : bidir : 3.3-V LVTTL : : 1A : Y
+led[3] : 14 : output : 3.3-V LVTTL : : 1A : Y
+gpio_jtagen : 15 : bidir : 3.3-V LVTTL : : 1B : Y
+~ALTERA_TMS~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 16 : input : 3.3 V Schmitt Trigger : : 1B : N
+led[2] : 17 : output : 3.3-V LVTTL : : 1B : Y
+~ALTERA_TCK~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 18 : input : 3.3 V Schmitt Trigger : : 1B : N
+~ALTERA_TDI~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 19 : input : 3.3 V Schmitt Trigger : : 1B : N
+~ALTERA_TDO~ : 20 : output : 3.3-V LVTTL : : 1B : N
+spi_miso : 21 : bidir : 3.3-V LVTTL : : 1B : Y
+spi_mosi : 22 : bidir : 3.3-V LVTTL : : 1B : Y
+VCCIO1B : 23 : power : : 3.3V : 1B :
+RESERVED_INPUT_WITH_WEAK_PULLUP : 24 : : : : 1B :
+spi_clk : 25 : bidir : 3.3-V LVTTL : : 1B : Y
+clock_48 : 26 : input : 3.3-V LVTTL : : 2 : Y
+rtc_32khz : 27 : input : 3.3-V LVTTL : : 2 : Y
+esp_io0 : 28 : bidir : 3.3-V LVTTL : : 2 : Y
+spi_cs_esp_n : 29 : bidir : 3.3-V LVTTL : : 2 : Y
+led[1] : 30 : output : 3.3-V LVTTL : : 2 : Y
+VCCIO2 : 31 : power : : 3.3V : 2 :
+tty_rxd : 32 : output : 3.3-V LVTTL : : 2 : Y
+sr_clk : 33 : output : 3.3-V LVTTL : : 2 : Y
+VCCA2 : 34 : power : : 3.0V/3.3V : :
+VCCA1 : 35 : power : : 3.0V/3.3V : :
+VCC_ONE : 36 : power : : 3.0V/3.3V : :
+VCC_ONE : 37 : power : : 3.0V/3.3V : :
+sd_dat[2] : 38 : bidir : 3.3-V LVTTL : : 3 : Y
+sd_dat[3] : 39 : bidir : 3.3-V LVTTL : : 3 : Y
+VCCIO3 : 40 : power : : 3.3V : 3 :
+sd_cmd : 41 : output : 3.3-V LVTTL : : 3 : Y
+GND : 42 : gnd : : : :
+sr_a[6] : 43 : output : 3.3-V LVTTL : : 3 : Y
+sr_a[7] : 44 : output : 3.3-V LVTTL : : 3 : Y
+sr_a[8] : 45 : output : 3.3-V LVTTL : : 3 : Y
+sr_a[9] : 46 : output : 3.3-V LVTTL : : 3 : Y
+sr_a[11] : 47 : output : 3.3-V LVTTL : : 3 : Y
+sd_clk : 48 : output : 3.3-V LVTTL : : 3 : Y
+VCCIO3 : 49 : power : : 3.3V : 3 :
+sr_a[12] : 50 : output : 3.3-V LVTTL : : 3 : Y
+VCC_ONE : 51 : power : : 3.0V/3.3V : :
+sr_cke : 52 : output : 3.3-V LVTTL : : 3 : Y
+GND : 53 : gnd : : : :
+sd_dat[0] : 54 : bidir : 3.3-V LVTTL : : 3 : Y
+tty_txd : 55 : input : 3.3-V LVTTL : : 3 : Y
+sr_dqm[1] : 56 : output : 3.3-V LVTTL : : 3 : Y
+sr_dq[8] : 57 : bidir : 3.3-V LVTTL : : 3 : Y
+sr_dq[9] : 58 : bidir : 3.3-V LVTTL : : 3 : Y
+sr_dq[10] : 59 : bidir : 3.3-V LVTTL : : 3 : Y
+sr_dq[11] : 60 : bidir : 3.3-V LVTTL : : 3 : Y
+i2c_scl : 61 : bidir : 3.3-V LVTTL : : 4 : Y
+i2c_sda : 62 : bidir : 3.3-V LVTTL : : 4 : Y
+GND : 63 : gnd : : : :
+sr_dq[12] : 64 : bidir : 3.3-V LVTTL : : 4 : Y
+sr_dq[13] : 65 : bidir : 3.3-V LVTTL : : 4 : Y
+sd_dat[1] : 66 : bidir : 3.3-V LVTTL : : 4 : Y
+VCCIO4 : 67 : power : : 3.3V : 4 :
+GND : 68 : gnd : : : :
+sr_dq[14] : 69 : bidir : 3.3-V LVTTL : : 4 : Y
+sr_dq[15] : 70 : bidir : 3.3-V LVTTL : : 4 : Y
+VCCA5 : 71 : power : : 3.0V/3.3V : :
+VCC_ONE : 72 : power : : 3.0V/3.3V : :
+VCC_ONE : 73 : power : : 3.0V/3.3V : :
+sr_a[4] : 74 : output : 3.3-V LVTTL : : 5 : Y
+sr_dq[0] : 75 : bidir : 3.3-V LVTTL : : 5 : Y
+sr_dq[1] : 76 : bidir : 3.3-V LVTTL : : 5 : Y
+sr_dq[2] : 77 : bidir : 3.3-V LVTTL : : 5 : Y
+abc_nmi : 78 : output : 3.3-V LVTTL : : 5 : Y
+sr_dq[3] : 79 : bidir : 3.3-V LVTTL : : 5 : Y
+abc_rdy_n : 80 : output : 3.3-V LVTTL : : 5 : Y
+sr_dq[4] : 81 : bidir : 3.3-V LVTTL : : 5 : Y
+VCCIO5 : 82 : power : : 3.3V : 5 :
+GND : 83 : gnd : : : :
+sr_dq[5] : 84 : bidir : 3.3-V LVTTL : : 5 : Y
+sr_a[3] : 85 : output : 3.3-V LVTTL : : 5 : Y
+sr_a[2] : 86 : output : 3.3-V LVTTL : : 5 : Y
+sr_a[1] : 87 : output : 3.3-V LVTTL : : 5 : Y
+abc_800 : 88 : input : 3.3-V LVTTL : : 6 : Y
+sr_a[0] : 89 : output : 3.3-V LVTTL : : 6 : Y
+abc_clk : 90 : input : 3.3-V LVTTL : : 6 : Y
+sr_a[10] : 91 : output : 3.3-V LVTTL : : 6 : Y
+sr_ba[1] : 92 : output : 3.3-V LVTTL : : 6 : Y
+sr_ba[0] : 93 : output : 3.3-V LVTTL : : 6 : Y
+VCCIO6 : 94 : power : : 3.3V : 6 :
+GND : 95 : gnd : : : :
+sr_cs_n : 96 : output : 3.3-V LVTTL : : 6 : Y
+spi_cs_flash_n : 97 : bidir : 3.3-V LVTTL : : 6 : Y
+sr_ras_n : 98 : output : 3.3-V LVTTL : : 6 : Y
+sr_cas_n : 99 : output : 3.3-V LVTTL : : 6 : Y
+sr_we_n : 100 : output : 3.3-V LVTTL : : 6 : Y
+sr_dqm[0] : 101 : output : 3.3-V LVTTL : : 6 : Y
+sr_dq[7] : 102 : bidir : 3.3-V LVTTL : : 6 : Y
+VCCIO6 : 103 : power : : 3.3V : 6 :
+GND : 104 : gnd : : : :
+sr_dq[6] : 105 : bidir : 3.3-V LVTTL : : 6 : Y
+tty_rts : 106 : input : 3.3-V LVTTL : : 6 : Y
+VCCA3 : 107 : power : : 3.0V/3.3V : :
+VCC_ONE : 108 : power : : 3.0V/3.3V : :
+VCC_ONE : 109 : power : : 3.0V/3.3V : :
+abc_ad[7] : 110 : bidir : 3.3-V LVTTL : : 7 : Y
+abc_ad[6] : 111 : bidir : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : 112 : : : : 7 :
+abc_ad[5] : 113 : bidir : 3.3-V LVTTL : : 7 : Y
+abc_ad[4] : 114 : bidir : 3.3-V LVTTL : : 7 : Y
+VCC_ONE : 115 : power : : 3.0V/3.3V : :
+GND : 116 : gnd : : : :
+VCCIO7 : 117 : power : : 3.3V : 7 :
+abc_ad[3] : 118 : bidir : 3.3-V LVTTL : : 7 : Y
+abc_ad[2] : 119 : bidir : 3.3-V LVTTL : : 7 : Y
+abc_ad[1] : 120 : bidir : 3.3-V LVTTL : : 8 : Y
+abc_ad[0] : 121 : bidir : 3.3-V LVTTL : : 8 : Y
+abc_xm_n : 122 : output : 3.3-V LVTTL : : 8 : Y
+abc_memwr_n : 123 : input : 3.3-V LVTTL : : 8 : Y
+abc_int_n : 124 : output : 3.3-V LVTTL : : 8 : Y
+GND : 125 : gnd : : : :
+sr_a[5] : 126 : output : 3.3-V LVTTL : : 8 : N
+abc_resin : 127 : output : 3.3-V LVTTL : : 8 : Y
+VCCIO8 : 128 : power : : 3.3V : 8 :
+RESERVED_INPUT_WITH_WEAK_PULLUP : 129 : : : : 8 :
+abc_iowr_n : 130 : input : 3.3-V LVTTL : : 8 : Y
+abc_iord_n : 131 : input : 3.3-V LVTTL : : 8 : Y
+abc_memrd_n : 132 : input : 3.3-V LVTTL : : 8 : Y
+GND : 133 : gnd : : : :
+abc_adsel[1] : 134 : output : 3.3-V LVTTL : : 8 : Y
+abc_adsel[0] : 135 : output : 3.3-V LVTTL : : 8 : Y
+RESERVED_INPUT_WITH_WEAK_PULLUP : 136 : : : : 8 :
+GND : 137 : gnd : : : :
+tty_cts : 138 : output : 3.3-V LVTTL : : 8 : Y
+VCCIO8 : 139 : power : : 3.3V : 8 :
+tty_dtr : 140 : input : 3.3-V LVTTL : : 8 : Y
+rtc_int_n : 141 : input : 3.3-V LVTTL : : 8 : Y
+GND : 142 : gnd : : : :
+VCCA4 : 143 : power : : 3.0V/3.3V : :
+VCC_ONE : 144 : power : : 3.0V/3.3V : :