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Diffstat (limited to 'max80.sdc')
-rw-r--r-- | max80.sdc | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/max80.sdc b/max80.sdc new file mode 100644 index 0000000..3523685 --- /dev/null +++ b/max80.sdc @@ -0,0 +1,37 @@ +# -*- tcl -*- + +# Clock constraints + +# Note: round up +create_clock -name "clock_48" -period 20.834ns [get_ports {clock_48}] +create_clock -name "rtc_32khz" -period 30517.579ns [get_ports {rtc_32khz}] + +# Automatically constrain PLL and other generated clocks +derive_pll_clocks + +# Automatically calculate clock uncertainty to jitter and other effects. +derive_clock_uncertainty + +# Reset isn't actually a clock, but Quartus thinks it is +create_generated_clock -name rst_n \ + -source [get_nets pll|*clk\[1\]] \ + [get_registers rst_n] + +# Reset is asynchronous with everything as far as we are concerned. +set main_clocks [get_clocks pll|*] +set_clock_groups -asynchronous \ + -group $main_clocks \ + -group [get_clocks rst_n] + +# Anything that feeds into a synchronizer is by definition +# asynchronous, but encode it as allowing multicycle of one +# clock, to limit the possible skew (but it is of course not possible +# to eliminate it...) +set synchro_inputs [get_registers *|synchronizer:*|qreg0*] +set_multicycle_path -from [all_clocks] -to $synchro_inputs \ + -start -setup 2 +set_multicycle_path -from [all_clocks] -to $synchro_inputs \ + -start -hold -1 + +# Don't report signaltap clock problems... +set_false_path -to [get_registers sld_signaltap:*] |