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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2019  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and any partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
# Date created = 13:01:33  February 22, 2021
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		max80_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M16SCE144C8G
set_global_assignment -name TOP_LEVEL_ENTITY max80
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:01:33  FEBRUARY 22, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE EQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name DEVICE_MIGRATION_LIST "10M16SCE144C8G,10M08SCE144C8G,10M04SCE144C8G,10M25SCE144C8G"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VCCA_USER_VOLTAGE 3.3V
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 3.3V
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SDC_FILE max80.sdc
set_global_assignment -name SYSTEMVERILOG_FILE max80.sv
set_global_assignment -name QIP_FILE ip/pll.qip
set_global_assignment -name SAFE_STATE_MACHINE ON
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name HDL_MESSAGE_LEVEL LEVEL3
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING "PACK ALL IO REGISTERS"
set_global_assignment -name WEAK_PULL_UP_RESISTOR ON
set_location_assignment PIN_110 -to abc_ad[7]
set_location_assignment PIN_111 -to abc_ad[6]
set_location_assignment PIN_113 -to abc_ad[5]
set_location_assignment PIN_114 -to abc_ad[4]
set_location_assignment PIN_118 -to abc_ad[3]
set_location_assignment PIN_119 -to abc_ad[2]
set_location_assignment PIN_120 -to abc_ad[1]
set_location_assignment PIN_121 -to abc_ad[0]
set_location_assignment PIN_134 -to abc_adsel[1]
set_location_assignment PIN_135 -to abc_adsel[0]
set_location_assignment PIN_90 -to abc_clk
set_location_assignment PIN_124 -to abc_int_n
set_location_assignment PIN_131 -to abc_iord_n
set_location_assignment PIN_130 -to abc_iowr_n
set_location_assignment PIN_132 -to abc_memrd_n
set_location_assignment PIN_123 -to abc_memwr_n
set_location_assignment PIN_78 -to abc_nmi
set_location_assignment PIN_127 -to abc_resin
set_location_assignment PIN_122 -to abc_xm_n
set_location_assignment PIN_26 -to clock_48
set_location_assignment PIN_6 -to esp_int
set_location_assignment PIN_28 -to esp_io0
set_location_assignment PIN_7 -to gpio[5]
set_location_assignment PIN_8 -to gpio[4]
set_location_assignment PIN_10 -to gpio[3]
set_location_assignment PIN_11 -to gpio[2]
set_location_assignment PIN_12 -to gpio[1]
set_location_assignment PIN_13 -to gpio[0]
set_location_assignment PIN_15 -to gpio_jtagen
set_location_assignment PIN_61 -to i2c_scl
set_location_assignment PIN_62 -to i2c_sda
set_location_assignment PIN_14 -to led[3]
set_location_assignment PIN_17 -to led[2]
set_location_assignment PIN_30 -to led[1]
set_location_assignment PIN_27 -to rtc_32khz
set_location_assignment PIN_141 -to rtc_int_n
set_location_assignment PIN_48 -to sd_clk
set_location_assignment PIN_88 -to sd_cmd
set_location_assignment PIN_39 -to sd_dat[3]
set_location_assignment PIN_38 -to sd_dat[2]
set_location_assignment PIN_66 -to sd_dat[1]
set_location_assignment PIN_54 -to sd_dat[0]
set_location_assignment PIN_25 -to spi_clk
set_location_assignment PIN_29 -to spi_cs_esp_n
set_location_assignment PIN_21 -to spi_miso
set_location_assignment PIN_22 -to spi_mosi
set_location_assignment PIN_89 -to sr_a[0]
set_location_assignment PIN_87 -to sr_a[1]
set_location_assignment PIN_86 -to sr_a[2]
set_location_assignment PIN_85 -to sr_a[3]
set_location_assignment PIN_74 -to sr_a[4]
set_location_assignment PIN_41 -to sr_a[5]
set_location_assignment PIN_43 -to sr_a[6]
set_location_assignment PIN_44 -to sr_a[7]
set_location_assignment PIN_45 -to sr_a[8]
set_location_assignment PIN_46 -to sr_a[9]
set_location_assignment PIN_91 -to sr_a[10]
set_location_assignment PIN_47 -to sr_a[11]
set_location_assignment PIN_50 -to sr_a[12]
set_location_assignment PIN_93 -to sr_ba[0]
set_location_assignment PIN_92 -to sr_ba[1]
set_location_assignment PIN_99 -to sr_cas_n
set_location_assignment PIN_52 -to sr_cke
set_location_assignment PIN_33 -to sr_clk
set_location_assignment PIN_96 -to sr_cs_n
set_location_assignment PIN_75 -to sr_dq[0]
set_location_assignment PIN_76 -to sr_dq[1]
set_location_assignment PIN_77 -to sr_dq[2]
set_location_assignment PIN_79 -to sr_dq[3]
set_location_assignment PIN_81 -to sr_dq[4]
set_location_assignment PIN_84 -to sr_dq[5]
set_location_assignment PIN_105 -to sr_dq[6]
set_location_assignment PIN_102 -to sr_dq[7]
set_location_assignment PIN_57 -to sr_dq[8]
set_location_assignment PIN_58 -to sr_dq[9]
set_location_assignment PIN_59 -to sr_dq[10]
set_location_assignment PIN_60 -to sr_dq[11]
set_location_assignment PIN_64 -to sr_dq[12]
set_location_assignment PIN_65 -to sr_dq[13]
set_location_assignment PIN_69 -to sr_dq[14]
set_location_assignment PIN_70 -to sr_dq[15]
set_location_assignment PIN_101 -to sr_dqm[0]
set_location_assignment PIN_56 -to sr_dqm[1]
set_location_assignment PIN_98 -to sr_ras_n
set_location_assignment PIN_100 -to sr_we_n
set_location_assignment PIN_138 -to tty_cts
set_location_assignment PIN_140 -to tty_dtr
set_location_assignment PIN_106 -to tty_rts
set_location_assignment PIN_32 -to tty_rxd
set_location_assignment PIN_55 -to tty_txd
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name GENERATE_JBC_FILE ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_location_assignment PIN_97 -to spi_cs_flash_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to sr_clk
set_location_assignment PIN_80 -to abc_rdy_n

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top