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//
// Top level module for the FPGA on the MAX80 board by
// Per Mårtensson and H. Peter Anvin
//
// Sharing JTAG pins (via JTAGEN)
`undef SHARED_JTAG
module max80 (
// Clock oscillator
input clock_48, // 48 MHz
// ABC-bus
input abc_clk, // ABC-bus 3 MHz clock
output [1:0] abc_adsel, // A/D bus select
inout [7:0] abc_ad, // Multiplexed A/D bus
input abc_memwr_n, // Memory write strobe
input abc_memrd_n, // Memory read strobe
input abc_iowr_n, // I/O write strobe
input abc_iord_n, // I/O read strobe
output abc_rdy_n, // RDY# (not WAIT)
output abc_resin, // System reset request
output abc_nmi, // System NMI request (ABC800 only)
output abc_int_n, // System INT request
output abc_xm_n, // System memory override (ABC800 only)
input abc_800, // ABC800 (not ABC80)
// SDRAM bus
output sr_clk,
output sr_cke,
output [1:0] sr_ba, // Bank address
output [12:0] sr_a, // Address within bank
inout [15:0] sr_dq, // Also known as D or IO
output [1:0] sr_dqm, // DQML and DQMH
output sr_cs_n,
output sr_we_n,
output sr_cas_n,
output sr_ras_n,
// SD card
output sd_clk,
output sd_cmd,
inout [3:0] sd_dat,
// USB serial (naming is FPGA as DCE)
input tty_txd,
output tty_rxd,
input tty_rts,
output tty_cts,
input tty_dtr,
// SPI bus (connected to ESP32 so can be bidirectional)
inout spi_clk,
inout spi_miso,
inout spi_mosi,
inout spi_cs_esp_n, // ESP32 IO10
inout spi_cs_flash_n,
// Other ESP32 connections
inout esp_io0, // ESP32 IO00
inout esp_int, // ESP32 IO09
// I2C bus (RTC and external)
inout i2c_scl,
inout i2c_sda,
input rtc_32khz,
input rtc_int_n,
// LED
output [3:1] led,
// GPIO pins
inout [5:0] gpio,
`ifdef SHARED_JTAG
// Sharable JTAG
inout gpio_tms,
inout gpio_tck,
inout gpio_tdi,
inout gpio_tdo,
`else
// JTAG not shared, JTAGEN is GPIO
inout gpio_jtagen
`endif
);
// Constants for abc_adsel (selects use of abc_ad)
wire [1:0] ad_din = 2'b00; // Data bus input
wire [1:0] ad_dout = 2'b01; // Data bus output
wire [1:0] ad_ah = 2'b10; // Address [15:8]
wire [1:0] ad_al = 2'b11; // Address [7:0]
// PLL and reset
parameter reset_pow2 = 12; // Assert internal reset for 4096 cycles
reg [reset_pow2-1:0] rst_ctr;
reg rst_n; // Internal reset
wire pll_locked;
wire clk; // System clock
pll pll (
.areset ( 1'b0 ),
.inclk0 ( clock_48 ),
.c0 ( sr_clk ), // SDRAM clock (144 MHz)
.c1 ( clk ), // System clock (96 MHz)
.locked ( pll_locked ),
.phasestep ( 1'b0 ),
.phasecounterselect ( 3'b0 ),
.phaseupdown ( 1'b1 ),
.scanclk ( 1'b0 ),
.phasedone ( )
);
always @(negedge pll_locked or posedge clk)
if (~pll_locked)
begin
rst_ctr <= 1'b0;
rst_n <= 1'b0;
end
else
begin
{ rst_n, rst_ctr } <= rst_ctr + ~rst_n;
end
// Unused device stubs - remove when used
// ABC bus
assign abc_adsel = ad_al;
assign abc_ad = 8'hzz;
assign abc_rdy_n = 1'b0;
assign abc_resin = ~rst_n;
assign abc_nmi = 1'b0;
assign abc_int_n = 1'b1;
assign abc_xm_n = 1'b1;
// SDRAM bus
assign sr_cke = 1'b0;
assign sr_ba = 2'b0;
assign sr_a = 13'b0;
assign sr_dq = 16'b0;
assign sr_dqm = 2'b11;
assign sr_cs_n = 1'b1;
assign sr_we_n = 1'b1;
assign sr_cas_n = 1'b1;
assign sr_ras_n = 1'b1;
// SD card
assign sd_clk = 1'b1;
assign sd_cmd = 1'b1;
assign sd_dat = 4'hz;
// USB serial
assign tty_rxd = 1'b1;
assign tty_cts = 1'b1;
// SPI bus (free for ESP32)
assign spi_clk = 1'bz;
assign spi_miso = 1'bz;
assign spi_mosi = 1'bz;
assign spi_cs_esp_n = 1'bz;
assign spi_cs_flash_n = 1'bz;
// ESP32
assign esp_io0 = 1'bz;
assign esp_int = 1'bz;
// I2C
assign i2c_scl = 1'bz;
assign i2c_sda = 1'bz;
// LED
assign led = 3'b000;
// GPIO
assign gpio = 6'bzzzzzz;
`ifdef SHARED_JTAG
// Sharable JTAG
assign gpio_tms = 1'bz;
assign gpio_tck = 1'bz;
assign gpio_tdi = 1'bz;
assign gpio_tdo = 1'bz;
`else
// JTAG not shared, JTAGEN is GPIO
assign gpio_jtagen = 1'bz;
`endif
endmodule
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