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// -----------------------------------------------------------------------
//   
//   Copyright 2003-2010 H. Peter Anvin - All Rights Reserved
//
//   This program is free software; you can redistribute it and/or modify
//   it under the terms of the GNU General Public License as published by
//   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
//   Bostom MA 02111-1307, USA; either version 2 of the License, or
//   (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------

//
// de1.v
//
// Top-level module for ABC8000 DE1 implementation for the
// Terasic DE1/Altera Cyclone II Starter Board
//
module abc8000_de1 (
	      input  	    clock_50,	// 50 MHz clock
	      input   [1:0] clock_24,	// 24 MHz clock (on two pins)
	      input   [1:0] clock_27,	// 27 MHz clock (on two pins)
	      input         ext_clock,	// External clock input

              inout         ps2_clk,	// PS/2 keyboard clock
              inout         ps2_dat,	// PS/2 keyboard data
	      
	      output  [9:0] ledr,	// Red LEDs
	      output  [7:0] ledg,	// Green LEDs
	      output  [6:0] s7_0,	// 7-segment LEDs
	      output  [6:0] s7_1,	// 7-segment LEDs
	      output  [6:0] s7_2,	// 7-segment LEDs
	      output  [6:0] s7_3,	// 7-segment LEDs
	      
	      input   [3:0] key_n,	// Pushbutton switches
	      input   [9:0] sw,		// Slide switches

	      output        fl_rst_n,   // Flash ROM RST#
	      output        fl_ce_n,    // Flash ROM CE#
	      output        fl_oe_n,	// Flash ROM OE#
	      output        fl_we_n,    // Flash ROM WE#
	      output [21:0] fl_a,       // Flash ROM address bus
	      inout   [7:0] fl_dq,      // Flash ROM data bus

	      output  [1:0] dram_ba,    // SDRAM bank selects
	      output        dram_ras_n,	// SDRAM RAS#
	      output        dram_cas_n,	// SDRAM CAS#
	      output        dram_cke,   // SDRAM clock enable
	      output        dram_clk,   // SDRAM clock
	      output        dram_cs_n,  // SDRAM CS#
	      output        dram_we_n,  // SDRAM WE#
	      output  [1:0] dram_dqm,   // SDRAM DQM (per byte)
	      output [11:0] dram_a,     // SDRAM address bus
	      inout  [15:0] dram_dq,    // SDRAM data bus
	      
	      output        sram_ce_n,	// SRAM CE#
	      output        sram_oe_n,	// SRAM OE#
	      output        sram_we_n,	// SRAM WE#
	      output  [1:0] sram_be_n,  // SRAM UB#, LB#
	      output [17:0] sram_a,	// SRAM address bus
	      inout  [15:0] sram_dq,    // SRAM data bus

	      output        sd_clk,     // SD card clock
	      inout         sd_cmd,     // SD card DI/MOSI/CMD
	      inout         sd_dat0,    // SD card SO/MISO/DAT0
	      inout         sd_dat3,    // SD card CS#/CD/DAT3
	      
	      output        uart_txd,   // RS232 port TxD
	      input         uart_rxd,   // RS232 port RxD
	      
	      output  [3:0] vga_r,	// VGA red
	      output  [3:0] vga_g,      // VGA green
	      output  [3:0] vga_b,	// VGA blue
	      output        vga_hs,	// VGA horz sync
	      output        vga_vs, 	// VGA vert sync

	      output        aud_xck,    // Audio master clock
	      output        aud_bclk,	// Audio bitclock
	      output        aud_dacdat, // Audio DAC data
	      output        aud_daclrck, // Audio DAC framing
	      input         aud_adcdat, // Audio ADC data
	      output        aud_adclrck, // Audio ADC framing

	      inout	    i2c_scl,	// I2C SCK line
	      inout         i2c_sda,	// I2C SDA line

	      inout  [35:0] gpio_0,   	// GPIO headers
	      inout  [35:0] gpio_1	// GPIO headers
	      );

   // ------------------------------------------------------------------------
   //  PLLs and clock distribution
   // ------------------------------------------------------------------------

   wire 	 cpu_clk;	//  12.5 MHz
   wire          sys_clk;	//    25 MHz
   wire		 video_clk;	//    25 MHz
   wire 	 sdram_clk;	//   125 MHz
   wire 	 audio_clk;	//  12.5 MHz
   wire 	 pll1_locked;

   
   pll1 pll1 (
	      .areset ( 1'b0 ),
	      .inclk0 ( clock_50 ),	// 50 MHz input clock
	      .c0 ( cpu_clk ),		// x1/4  = 12.5 MHz
	      .c1 ( sys_clk ),		// x1/2  = 25.0 MHz
	      .c2 ( sdram_clk ),	// x5/2  =  125 MHz
	      .locked ( pll1_locked )
	      );
   
   assign video_clk = sys_clk;
   assign audio_clk = cpu_clk;
   
   // ------------------------------------------------------------------------
   //  Reset - synchronization and pulse stretch
   // ------------------------------------------------------------------------
`define RESET_WIDTH 8		// 2^8 = 256 cycles minimum width
   reg [`RESET_WIDTH:0] rst_ctr = 0;
   wire 		rst_n = rst_ctr[`RESET_WIDTH];
   reg 			power_rst_n = 1'b0;
   wire 		reset_key;
   wire		        do_reset = reset_key | ~pll1_locked;
   
   always @(posedge sys_clk)
     if (do_reset)
       rst_ctr <= 0;
     else if (~rst_n)
       rst_ctr <= rst_ctr + 1'b1;

   always @(posedge sys_clk)
     power_rst_n <= 1'b1;

   // ------------------------------------------------------------------------
   //  Keys and switches - synchronize and debounce/deglitch to 10 us
   // ------------------------------------------------------------------------

   wire [9:0] 		sw_d;
   wire [3:0] 		key_d;
   
   debounce #(.width(10), .count(7)) debounce_sw
     (
      .clk	( cpu_clk ),	// 12.5 MHz
      .in	( sw ),
      .out	( sw_d ),
      .strobe	( )
      );
   
   debounce #(.width(4), .count(7)) debounce_key
     (
      .clk	( cpu_clk ),	// 12.5 MHz
      .in	( ~key_n ),
      .out	( key_d ),
      .strobe	( )
      );

   assign reset_key = key_d[2];
   
   // ------------------------------------------------------------------------
   //  TG68 processor
   // ------------------------------------------------------------------------

   wire [15:0] 		cpu_di;
   wire [15:0] 		cpu_do;
   wire [31:0] 		cpu_a;
   wire 		cpu_as_n;
   wire 		cpu_dtack_n;
   wire [1:0] 		cpu_be_n; // Modern terminology: byte enables
   wire 		cpu_r_wn;
   wire [2:0] 		cpu_ipl_n;

   tg68 cpu (
	     .reset ( rst_n ),
	     .clk ( cpu_clk ),
	     .clkena_in ( 1'b1 ),
	     .data_in ( cpu_di ),
	     .IPL ( cpu_ipl_n ),
	     .avec ( 1'b1 ),
	     .dtack ( cpu_dtack_n ),
	     .addr ( cpu_a ),
	     .data_out ( cpu_do ),
	     .as ( cpu_as_n ),
	     .uds ( cpu_be_n[1] ), // Bigendian, this is A0 = 0!
	     .lds ( cpu_be_n[0] ), // Bigendian, this is A0 = 1!
	     .rw ( cpu_r_wn ),
	     .drive_data ( )
	     );
   
   // ------------------------------------------------------------------------
   //  System bus
   // ------------------------------------------------------------------------

   reg 			boot_mode;
   reg [15:0] 		cpu_a_dev;

   wire	msel_sdram      = ~cpu_as_n & (~boot_mode | ~cpu_r_wn) & ~cpu_a[23];
   wire msel_flash      = ~cpu_as_n & ((cpu_a[23:22] == 2'b10) |
 		          (boot_mode & cpu_r_wn & ~cpu_a[23]));
   // c00000-dfffff unused/reserved (expansion bus?)
   wire msel_video      = ~cpu_as_n & (cpu_a[23:20] == 4'b1110);
   wire [15:0] msel_dev = {16{~cpu_as_n}} & cpu_a_dev;

   //
   // Device address decode - this takes place *before* AS# is asserted,
   // so don't include cpu_as_n in these equations
   //
   always @(negedge rst_n or posedge sys_clk)
     if (~rst_n)
       cpu_a_dev <= 16'h0000;
     else
       case (cpu_a[23:16])
	 8'hf0: cpu_a_dev <= 16'h0001;
	 8'hf1: cpu_a_dev <= 16'h0002;
	 8'hf2: cpu_a_dev <= 16'h0004;
	 8'hf3: cpu_a_dev <= 16'h0008;
	 8'hf4: cpu_a_dev <= 16'h0010;
	 8'hf5: cpu_a_dev <= 16'h0020;
	 8'hf6: cpu_a_dev <= 16'h0040;
	 8'hf7: cpu_a_dev <= 16'h0080;
	 8'hf8: cpu_a_dev <= 16'h0100;
	 8'hf9: cpu_a_dev <= 16'h0200;
	 8'hfa: cpu_a_dev <= 16'h0400;
	 8'hfb: cpu_a_dev <= 16'h0800;
	 8'hfc: cpu_a_dev <= 16'h1000;
	 8'hfd: cpu_a_dev <= 16'h2000;
	 8'hfe: cpu_a_dev <= 16'h4000;
	 8'hff: cpu_a_dev <= 16'h8000;
	 default: cpu_a_dev <= 16'h0000;
       endcase // case(cpu_a[23:16])
   
   // ------------------------------------------------------------------------
   //  System control registers
   // ------------------------------------------------------------------------

   reg [7:0]   ledg_q;
   reg [31:0]  disp_s7;
   reg [31:0]  cycle_ctr;

   // Free-running CPU cycle counter
   always @(negedge rst_n or posedge cpu_clk)
     if (~rst_n)
       cycle_ctr <= 32'h0;
     else
       cycle_ctr <= cycle_ctr + 1;
   
   // Writing system control registers
   always @(negedge rst_n or posedge sys_clk)
     if (~rst_n)
       begin
	  boot_mode <= 1'b1;
	  disp_s7   <= 32'h00000000;
	  ledg_q    <= 8'h00;
       end
     else
       begin
	  if (msel_dev[0] & ~cpu_r_wn)
	    case (cpu_a[3:1])
	      3'b000:
		begin
		   if (~cpu_be_n[0])
		     boot_mode <= cpu_do[0];
		end
	      3'b001:
		begin
		   if (~cpu_be_n[0])
		     ledg_q <= cpu_do[15:8];
		end
	      3'b010:
		begin
		   if (~cpu_be_n[1])
		     disp_s7[31:24] <= cpu_do[15:8];
		   if (~cpu_be_n[0])
		     disp_s7[23:16] <= cpu_do[7:0];
		end
	      3'b011:
		begin
		   if (~cpu_be_n[1])
		     disp_s7[15:8]  <= cpu_do[15:8];
		   if (~cpu_be_n[0])
		     disp_s7[7:0]   <= cpu_do[7:0];
		end
	    endcase // case (cpu_a[3:1])
       end // else: !if(~rst_n)

   // Reading system control registers
   reg [15:0] sysctl_cpu_di;
   always @(negedge rst_n or posedge sys_clk)
     if (~rst_n)
       sysctl_cpu_di <= 16'hffff;
     else
       begin
	  sysctl_cpu_di <= 16'hffff;
	  
	  if (msel_dev[0] & cpu_r_wn)
	    case (cpu_a[3:1])
	      3'b000:
		sysctl_cpu_di <= { 15'b0, boot_mode };
	      3'b001:
		sysctl_cpu_di <= { 8'b0, ledg_q };
	      3'b010:
		sysctl_cpu_di <= disp_s7[31:16];
	      3'b011:
		sysctl_cpu_di <= disp_s7[15:0];
	      3'b100:
		sysctl_cpu_di <= cycle_ctr[31:16];
	      3'b101:
		sysctl_cpu_di <= cycle_ctr[15:0];
	      3'b110:
		sysctl_cpu_di <= { key_d, 2'b00, sw_d };
	    endcase // case (cpu_a[3:1])
       end

   assign ledg = ledg_q;
   
   assign s7_0 = ~disp_s7[6:0];
   assign s7_1 = ~disp_s7[14:8];
   assign s7_2 = ~disp_s7[22:16];
   assign s7_3 = ~disp_s7[30:24];

   // ------------------------------------------------------------------------
   //  68901 Multi-Function Peripheral, also interrupt controller
   // ------------------------------------------------------------------------

   wire        mfp_dtack_n;
   wire        mfp_irq_n;
   wire        mfp_clk;
   wire  [7:0] mfp_data_out;
   wire        mfp_data_en;
   wire [15:0] mfp_cpu_di = mfp_data_en ? { 8'hff, mfp_data_out } : 16'hffff;
   wire  [7:0] mfp_gpip_in;
   wire  [7:0] mfp_gpip_out;
   wire  [7:0] mfp_gpip_en;
   wire        mfp_rc;
   wire        mfp_tc;
   wire	       mfp_si;
   wire	       mfp_so;
   wire	       mfp_so_en;

   mfp_clk_gen mfp_clk_gen
     (
      .rst_n	( rst_n ),
      .sys_clk	( sys_clk ),
      .mfp_clk	( mfp_clk )
      );
   
   wf68901ip_top_soc mfp
     (
      .clk	( cpu_clk ),
      .resetn	( rst_n ),

      .dsn	( cpu_be_n[0] ),
      .csn	( ~msel_dev[14] ),
      .rwn	( cpu_r_wn ),
      .dtackn	( mfp_dtack_n ),

      .rs	( cpu_a[6:1] ),
      .data_in	( cpu_do[7:0] ),
      .data_out	( mfp_data_out ),
      .data_en  ( mfp_data_en ),
      .gpip_in	( mfp_gpip_in ),
      .gpip_out ( mfp_gpip_out ),
      .gpip_en  ( mfp_gpip_en ),
      
      .iackn	( ~msel_dev[15] ), // 0xffffxxxx = IACK
      .iein	( 1'b0 ),
      .ieon	( ),
      .irqn	( mfp_irq_n ),

      .xtal1	( mfp_clk ),
      .tai	( 1'b1 ),
      .tbi	( 1'b1 ),
      .tao	( ),
      .tbo	( ),
      .tco	( mfp_rc ),
      .tdo	( mfp_tc ),

      .rc	( mfp_rc ),
      .tc	( mfp_tc ),
      .si	( mfp_si ),
      .so	( mfp_so ),
      .so_en	( mfp_so_en ),

      .rrn	( ),
      .trn	( )
      );
   
   // ------------------------------------------------------------------------
   //  Flash ROM (readonly)
   // ------------------------------------------------------------------------

   reg   [1:0] fl_state;
   reg   [7:0] fl_hdata;
   wire [15:0] fl_cpu_di;
   
   // Flash ROM
   assign fl_rst_n = rst_n;
   assign fl_ce_n  = 1'b0;
   assign fl_oe_n  = 1'b0;
   assign fl_we_n  = 1'b1;
   assign fl_a     = { cpu_a[21:1], fl_state[1] };
   assign fl_dq    = 8'hzz;

   always @(negedge rst_n or posedge sys_clk)
     if (~rst_n)
       begin
	  fl_state   <= 2'b00;
	  fl_hdata   <= 8'hxx;
       end
     else
       case (fl_state)
	 2'b00:
	   if (msel_flash)
	     fl_state <= 2'b01;
	 2'b01:
	   begin
	      fl_hdata <= fl_dq;
	      fl_state <= 2'b10;
	   end
	 2'b10:
	   fl_state <= 2'b11;
	 2'b11:
	   if (~msel_flash)
	     fl_state <= 2'b00;
       endcase // case (fl_state)

   assign fl_cpu_di = msel_flash ? { fl_hdata, fl_dq } : 16'hffff;

   // ------------------------------------------------------------------------
   //  SDRAM controller
   // ------------------------------------------------------------------------

   // DRAM
   wire [15:0] sdram_cpu_di;
   wire        sdram_wait_n;
   
   assign dram_clk   = ~sdram_clk; // Opposite phase to the internal clock

   sdram sdram (
		.rst_n ( rst_n ),
		.sys_clk ( sys_clk ),

		.cpu_do ( cpu_do ),
		.cpu_di ( sdram_cpu_di ),
		.cpu_a ( cpu_a[22:1] ),
		.msel ( msel_sdram ),
		.cpu_be_n ( cpu_be_n ),
		.cpu_r_wn ( cpu_r_wn ),
		.cpu_wait_n ( sdram_wait_n ),

		.dram_clk ( sdram_clk ),
		.dram_cke ( dram_cke ),
		.dram_cs_n ( dram_cs_n ),
		.dram_ras_n ( dram_ras_n ),
		.dram_cas_n ( dram_cas_n ),
		.dram_we_n ( dram_we_n ),
		.dram_dqm ( dram_dqm ),
		.dram_ba ( dram_ba ),
		.dram_a ( dram_a ),
		.dram_dq ( dram_dq )
		);

   // ------------------------------------------------------------------------
   //  Audio chip
   // ------------------------------------------------------------------------

   wire [15:0] audio_cpu_di;
   wire        audio_wait_n;

   sound sound (
		.rst_n		( rst_n ),
		.clk		( audio_clk ),
		.msel		( msel_dev[3] & ~cpu_be_n[1] ),
		.cpu_a		( cpu_a[1] ),
		.cpu_r_wn	( cpu_r_wn ),
		.cpu_do		( cpu_do[15:8] ),
		.cpu_di		( audio_cpu_di[15:8] ),
		.cpu_wait_n	( audio_wait_n ),
		.i2s_dat	( aud_dacdat ),
		.i2s_lrck	( aud_daclrck ),
		.i2c_scl	( i2c_scl ),
		.i2c_sda	( i2c_sda )
		);

   assign audio_cpu_di[7:0] = 8'hff; // 8-bit device
   
   // Drive the output clocks via DDR buffers for better jitter performance
   ddio_out aud_xck_buf (
		     .datain_l	( 1'b0 ),
		     .datain_h	( 1'b1 ),
		     .oe	( 1'b1 ),
		     .outclock	( audio_clk ),
		     .dataout	( aud_xck )
		     );
   ddio_out aud_bclk_buf (
		      .datain_l ( 1'b0 ),
		      .datain_h ( 1'b1 ),
		      .oe	( 1'b1 ),
		      .outclock	( audio_clk ),
		      .dataout	( aud_bclk )
		      );

   assign    aud_adclrck = aud_daclrck;

   // ------------------------------------------------------------------------
   //  SD card interface
   // ------------------------------------------------------------------------

   wire [15:0] sdcard_cpu_di;
   wire        sdcard_wait_n;
   
   sdcard sdcard (
		  .rst_n	( rst_n ),
		  .clk		( sys_clk ),

		  .sd_cs_n	( sd_dat3 ),
		  .sd_di	( sd_cmd ),
		  .sd_clk	( sd_clk ),
		  .sd_do	( sd_dat0 ),

		  // Terasic didn't hook up the Card Detect
		  // and Write Enable switches in the SD socket
		  // to FPGA pins, so we have to make do with
		  // manual switches.
		  .sd_cd_n	( ~sw_d[0] ),  // SW0 on for inserted
		  .sd_we_n	( sw_d[1] ),   // SW1 on for Write Protect

		  .cpu_do	( cpu_do ),
		  .cpu_di	( sdcard_cpu_di ),
		  .msel		( msel_dev[4] ),
		  .cpu_be_n	( cpu_be_n ),
		  .cpu_a	( cpu_a[7:2] ),
		  .cpu_r_wn	( cpu_r_wn ),
		  .cpu_wait_n	( sdcard_wait_n )
		  );

   // ------------------------------------------------------------------------
   //  Stubbed out external devices
   // ------------------------------------------------------------------------

   assign ledr = sw_d;
   
   // GPIOs
   assign gpio_0      = 36'hz_zzzz_zzzz;
   assign gpio_1      = 36'hz_zzzz_zzzz;

   // ------------------------------------------------------------------------
   //  Display unit
   // ------------------------------------------------------------------------

   wire [15:0] video_cpu_di;
   
   display display (
		    .rst_n ( rst_n ),
		    .clk ( video_clk ), // == sys_clk

		    .cpu_do ( cpu_do ),
		    .cpu_di ( video_cpu_di ),
		    .cpu_a ( cpu_a[18:1] ),
		    .msel_fb ( msel_video ),
		    .msel_ctl ( msel_dev[2] ),
		    .cpu_be_n ( cpu_be_n ),
		    .cpu_r_wn ( cpu_r_wn ),

		    .sram_ce_n ( sram_ce_n ),
		    .sram_oe_n ( sram_oe_n ),
		    .sram_we_n ( sram_we_n ),
		    .sram_be_n ( sram_be_n ),
		    .sram_a ( sram_a ),
		    .sram_dq ( sram_dq ),

		    .hblank_n ( mfp_gpip_in[7] ),
		    .vblank_n ( mfp_gpip_in[6] ),
		    
		    .vga_r ( vga_r ),
		    .vga_g ( vga_g ),
		    .vga_b ( vga_b ),
		    .vga_hs ( vga_hs ),
		    .vga_vs ( vga_vs )
		    );

   // ------------------------------------------------------------------------
   //  Serial port
   // ------------------------------------------------------------------------

   wire [15:0] serial_cpu_di;
   
   serial serial
     (
      .rst_n		( rst_n ),
      .clk		( sys_clk ),
      .tty_txd		( uart_txd ),
      .tty_rxd		( uart_rxd ),
      .msel		( msel_dev[1] & ~cpu_be_n[1] ),
      .cpu_a		( cpu_a[1] ),
      .cpu_do		( cpu_do[15:8] ),
      .cpu_di		( serial_cpu_di[15:8] ),
      .cpu_r_wn		( cpu_r_wn )
      );

   assign serial_cpu_di[7:0] = 8'hff; // Byte-sized device only

   // ------------------------------------------------------------------------
   //  Keyboard port
   // ------------------------------------------------------------------------

   wire [15:0] kbd_cpu_di;
   
   ps2 kbd
     (
      .rst_n		( rst_n ),
      .clk		( sys_clk ),
      .ps2_clk		( ps2_clk ),
      .ps2_dat		( ps2_dat ),
      .msel		( msel_dev[5] & ~cpu_be_n[1] ),
      .cpu_a		( cpu_a[1] ),
      .cpu_do		( cpu_do[15:8] ),
      .cpu_di		( kbd_cpu_di[15:8] ),
      .cpu_r_wn		( cpu_r_wn ),
      .irq_n		( mfp_gpip_in[0] )
      );

   assign kbd_cpu_di[7:0] = 8'hff; // Byte-sized device only

   // ------------------------------------------------------------------------
   //  CPU input multiplex
   // ------------------------------------------------------------------------

   assign cpu_di      = fl_cpu_di & serial_cpu_di & 
			sdram_cpu_di & video_cpu_di & audio_cpu_di &
			sysctl_cpu_di & sdcard_cpu_di &
	  		kbd_cpu_di & mfp_cpu_di;
   
   assign cpu_dtack_n = (cpu_as_n |
			 ~( sdram_wait_n & audio_wait_n & sdcard_wait_n
			    & ~(msel_dev[14] | msel_dev[15])))
   			& mfp_dtack_n;

   // MFP assigned to IPL 4, nothing else in use
   assign cpu_ipl_n = { mfp_irq_n, 2'b11 };
   
endmodule // abc8000_de1

// ------------------------------------------------------------------------
//  68901 Multi-Function Peripheral clock generation
// ------------------------------------------------------------------------

//
// The MFP is assumed to be connected to a 2.457600 MHz clock crystal,
// allowing all the usual baud rates up to 19200 bps, with synchronous
// operation up to 307200 bps.
//
//  2457600 = 2^15 * 3 * 5^2
// 25000000 = 2^6 * 5^8
//
// We multiply by 3072/15625, and then have a final stage to divide by
// 2 to generate as close to a 1:1 clock as is possible.
//
module mfp_clk_gen
  (
   input	rst_n,
   input	sys_clk,
   output	mfp_clk
   );
   
   reg [13:0] ctr;
   reg final;

   assign mfp_clk = final;
   
   always @(negedge rst_n or posedge sys_clk)
     if (~rst_n)
       begin
	  ctr   <= 14'd0;
	  final <= 1'b0;
       end
     else
       begin
	  if ( ctr < (14'd15625 - 14'd3072) )
	    begin
	       ctr <= ctr + 14'd3072;
	    end
	  else
	    begin
	       ctr   <= ctr - (14'd15625 - 14'd3072);
	       final <= ~final;
	    end
       end // else: !if(~rst_n)
endmodule // mfp_clk