summaryrefslogtreecommitdiffstats
path: root/sdcard.v
diff options
context:
space:
mode:
authorH. Peter Anvin <hpa@zytor.com>2010-10-28 20:15:43 -0700
committerH. Peter Anvin <hpa@zytor.com>2014-02-10 18:07:49 -0800
commitb6c4df01b757d62703f42316b3600558dc2ef2fa (patch)
treea9e4be3825e5d0543f576d7c72d5a6f8a189b08c /sdcard.v
parenta7a1d2dddcbeef0498cdb0c6b5142ec4a11fb62e (diff)
downloadabc8000-b6c4df01b757d62703f42316b3600558dc2ef2fa.tar.gz
abc8000-b6c4df01b757d62703f42316b3600558dc2ef2fa.tar.xz
abc8000-b6c4df01b757d62703f42316b3600558dc2ef2fa.zip
sdcard: correct the handling of byte lanes and byte enables
Write control used the wrong byte lane. sd_cmd should be an AND of the BE# signals, not an OR.
Diffstat (limited to 'sdcard.v')
-rw-r--r--sdcard.v6
1 files changed, 3 insertions, 3 deletions
diff --git a/sdcard.v b/sdcard.v
index dc1e535..e470048 100644
--- a/sdcard.v
+++ b/sdcard.v
@@ -78,7 +78,7 @@ module sdcard (
reg sd_crcstb; // Strobe for CRC generator
reg [6:0] sd_crc7; // CRC-7 generator
reg [15:0] sd_crc16; // CRC-16 generator
- wire sd_sel = msel & ~|cpu_be_n; // Byte enables come late!
+ wire sd_sel = msel & ~&cpu_be_n; // Byte enables come late!
wire sd_cmd = sd_sel & ~sd_active; // CPU command we can act on
reg sd_cmd_ok; // Valid CPU command received
wire sd_start = sd_cmd & cpu_a[5]; // Transaction begin
@@ -161,8 +161,8 @@ module sdcard (
if (sd_cmd)
begin
- if (~cpu_r_wn & cpu_a[0] & ~cpu_be_n[1])
- {sd_cs_n_reg, sd_slow} <= cpu_do[9:8];
+ if (~cpu_r_wn & cpu_a[0] & ~cpu_be_n[0])
+ {sd_cs_n_reg, sd_slow} <= cpu_do[1:0];
if (~cpu_r_wn & cpu_a[1] & ~cpu_be_n[1])
sd_shr_out[15:8] <= cpu_do[15:8];