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authorH. Peter Anvin <hpa@zytor.com>2010-10-21 09:16:27 -0700
committerH. Peter Anvin <hpa@zytor.com>2014-02-10 18:07:47 -0800
commitb859a80bae101c84951b67639f809f1bb7f2940f (patch)
tree13609f0f5082c2ad342acec5f25297b2d029424c /serial.v
parent93ff164ebffda8c58b16fb30e8db68430ec08e8e (diff)
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RTL: fix issues mostly related to endianness
Bigendian is really confusing, but it's particularly confusing at the hardware level, especially if you do littleendian bit numbering (which is now universal). In the case of 68000, it means byte 0 is in A15-A8, and triggers UDS# not LDS#.
Diffstat (limited to 'serial.v')
-rw-r--r--serial.v6
1 files changed, 3 insertions, 3 deletions
diff --git a/serial.v b/serial.v
index f48f199..eaeccf2 100644
--- a/serial.v
+++ b/serial.v
@@ -70,7 +70,7 @@ module serial (
// Status generation
wire rx_empty;
- wire [7:0] status = { 6'b0, ~rx_empty, tx_busy };
+ wire [7:0] status = { 6'b0, tx_busy, ~rx_empty };
wire [7:0] rx_cpu_data;
assign cpu_di = cpu_rd ? (cpu_a ? status : rx_cpu_data) : 8'hFF;
@@ -88,9 +88,9 @@ module serial (
baud_rate_ctr <= 0;
tx_data_sr <= ~9'b0;
tx_data_out <= 1'b1;
- tx_busy_ctr <= ~0;
+ tx_busy_ctr <= 4'd0;
cpu_wrd_q <= 1'b1;
- cpu_rdd_q <= 1'b1;
+ cpu_rdd_q <= 1'b1;
end
else
begin