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authorH. Peter Anvin <hpa@zytor.com>2010-10-23 19:14:28 -0700
committerH. Peter Anvin <hpa@zytor.com>2014-02-10 18:07:48 -0800
commit79a1a99aad9222b91ac7685ed6a160a63f57ceac (patch)
tree5a359666bcee37c7769169f00c5c6079bcafcb36 /ym2149
parent6c142b6137f87fcacfbb06ba0eff0c32a7ff7cc8 (diff)
downloadabc8000-79a1a99aad9222b91ac7685ed6a160a63f57ceac.tar.gz
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Sound generator YM2149, a.k.a. AY-3-8910/8192
Include and hook up the sound generator, doesn't seem to work yet though.
Diffstat (limited to 'ym2149')
-rw-r--r--ym2149/YM2149_linmix.vhd623
-rw-r--r--ym2149/YM2149_tb.vhd212
-rw-r--r--ym2149/YM2149_volmix.vhd583
-rw-r--r--ym2149/vol_table.vhd592
-rw-r--r--ym2149/vol_table_001.txt301
-rw-r--r--ym2149/vol_table_array.vhd540
6 files changed, 2851 insertions, 0 deletions
diff --git a/ym2149/YM2149_linmix.vhd b/ym2149/YM2149_linmix.vhd
new file mode 100644
index 0000000..41a82c3
--- /dev/null
+++ b/ym2149/YM2149_linmix.vhd
@@ -0,0 +1,623 @@
+--
+-- A simulation model of YM2149 (AY-3-8910 with bells on)
+
+-- Copyright (c) MikeJ - Jan 2005
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.fpgaarcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- Revision list
+--
+-- version 001 initial release
+--
+-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
+--
+-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
+-- vol 15 .. 0
+-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
+-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
+-- to produced all the required values.
+-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
+--
+-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
+-- accurate for designs where the outputs are buffered and not simply wired together.
+-- The ouput level is more complex in that case and requires a larger table.
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
+
+entity YM2149 is
+ port (
+ -- data bus
+ I_DA : in std_logic_vector(7 downto 0);
+ O_DA : out std_logic_vector(7 downto 0);
+ O_DA_OE_L : out std_logic;
+ -- control
+ I_A9_L : in std_logic;
+ I_A8 : in std_logic;
+ I_BDIR : in std_logic;
+ I_BC2 : in std_logic;
+ I_BC1 : in std_logic;
+ I_SEL_L : in std_logic;
+
+ O_AUDIO : out std_logic_vector(7 downto 0);
+ -- port a
+ I_IOA : in std_logic_vector(7 downto 0);
+ O_IOA : out std_logic_vector(7 downto 0);
+ O_IOA_OE_L : out std_logic;
+ -- port b
+ I_IOB : in std_logic_vector(7 downto 0);
+ O_IOB : out std_logic_vector(7 downto 0);
+ O_IOB_OE_L : out std_logic;
+
+ ENA : in std_logic; -- clock enable for higher speed operation
+ RESET_L : in std_logic;
+ CLK : in std_logic -- note 6 Mhz
+ );
+end;
+
+architecture RTL of YM2149 is
+ type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0);
+ type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
+
+ signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
+ signal noise_div : std_logic := '0';
+ signal ena_div : std_logic;
+ signal ena_div_noise : std_logic;
+ signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
+
+ -- registers
+ signal addr : std_logic_vector(7 downto 0);
+ signal busctrl_addr : std_logic;
+ signal busctrl_we : std_logic;
+ signal busctrl_re : std_logic;
+
+ signal reg : array_16x8;
+ signal env_reset : std_logic;
+ signal ioa_inreg : std_logic_vector(7 downto 0);
+ signal iob_inreg : std_logic_vector(7 downto 0);
+
+ signal noise_gen_cnt : std_logic_vector(4 downto 0);
+ signal noise_gen_op : std_logic;
+ signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
+ signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
+
+ signal env_gen_cnt : std_logic_vector(15 downto 0);
+ signal env_ena : std_logic;
+ signal env_hold : std_logic;
+ signal env_inc : std_logic;
+ signal env_vol : std_logic_vector(4 downto 0);
+
+ signal tone_ena_l : std_logic;
+ signal tone_src : std_logic;
+ signal noise_ena_l : std_logic;
+ signal chan_vol : std_logic_vector(4 downto 0);
+
+ signal dac_amp : std_logic_vector(7 downto 0);
+ signal audio_mix : std_logic_vector(9 downto 0);
+ signal audio_final : std_logic_vector(9 downto 0);
+begin
+ -- cpu i/f
+ p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
+ variable cs : std_logic;
+ variable sel : std_logic_vector(2 downto 0);
+ begin
+ -- BDIR BC2 BC1 MODE
+ -- 0 0 0 inactive
+ -- 0 0 1 address
+ -- 0 1 0 inactive
+ -- 0 1 1 read
+ -- 1 0 0 address
+ -- 1 0 1 inactive
+ -- 1 1 0 write
+ -- 1 1 1 read
+ busctrl_addr <= '0';
+ busctrl_we <= '0';
+ busctrl_re <= '0';
+
+ cs := '0';
+ if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
+ cs := '1';
+ end if;
+
+ sel := (I_BDIR & I_BC2 & I_BC1);
+ case sel is
+ when "000" => null;
+ when "001" => busctrl_addr <= '1';
+ when "010" => null;
+ when "011" => busctrl_re <= cs;
+ when "100" => busctrl_addr <= '1';
+ when "101" => null;
+ when "110" => busctrl_we <= cs;
+ when "111" => busctrl_addr <= '1';
+ when others => null;
+ end case;
+ end process;
+
+ p_oe : process(busctrl_re)
+ begin
+ -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
+ O_DA_OE_L <= not (busctrl_re);
+ end process;
+
+ --
+ -- CLOCKED
+ --
+ --p_waddr : process
+ --begin
+ ---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+ --wait until rising_edge(CLK);
+
+ --if (RESET_L = '0') then
+ --addr <= (others => '0');
+ --else
+ --if (busctrl_addr = '1') then
+ --addr <= I_DA;
+ --end if;
+ --end if;
+ --end process;
+
+ --p_wdata : process
+ --begin
+ ---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+ --wait until rising_edge(CLK);
+ --env_reset <= '0';
+
+ --if (RESET_L = '0') then
+ --reg <= (others => (others => '0'));
+ --env_reset <= '1';
+ --else
+ --env_reset <= '0';
+ --if (busctrl_we = '1') then
+ --case addr(3 downto 0) is
+ --when x"0" => reg(0) <= I_DA;
+ --when x"1" => reg(1) <= I_DA;
+ --when x"2" => reg(2) <= I_DA;
+ --when x"3" => reg(3) <= I_DA;
+ --when x"4" => reg(4) <= I_DA;
+ --when x"5" => reg(5) <= I_DA;
+ --when x"6" => reg(6) <= I_DA;
+ --when x"7" => reg(7) <= I_DA;
+ --when x"8" => reg(8) <= I_DA;
+ --when x"9" => reg(9) <= I_DA;
+ --when x"A" => reg(10) <= I_DA;
+ --when x"B" => reg(11) <= I_DA;
+ --when x"C" => reg(12) <= I_DA;
+ --when x"D" => reg(13) <= I_DA; env_reset <= '1';
+ --when x"E" => reg(14) <= I_DA;
+ --when x"F" => reg(15) <= I_DA;
+ --when others => null;
+ --end case;
+ --end if;
+ --end if;
+ --end process;
+
+ --
+ -- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock.
+ --
+ p_waddr : process(reset_l, busctrl_addr)
+ begin
+ -- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+ if (RESET_L = '0') then
+ addr <= (others => '0');
+ elsif falling_edge(busctrl_addr) then -- yuk
+ addr <= I_DA;
+ end if;
+ end process;
+
+ p_wdata : process(reset_l, busctrl_we, addr)
+ begin
+ if (RESET_L = '0') then
+ reg <= (others => (others => '0'));
+ elsif falling_edge(busctrl_we) then
+ case addr(3 downto 0) is
+ when x"0" => reg(0) <= I_DA;
+ when x"1" => reg(1) <= I_DA;
+ when x"2" => reg(2) <= I_DA;
+ when x"3" => reg(3) <= I_DA;
+ when x"4" => reg(4) <= I_DA;
+ when x"5" => reg(5) <= I_DA;
+ when x"6" => reg(6) <= I_DA;
+ when x"7" => reg(7) <= I_DA;
+ when x"8" => reg(8) <= I_DA;
+ when x"9" => reg(9) <= I_DA;
+ when x"A" => reg(10) <= I_DA;
+ when x"B" => reg(11) <= I_DA;
+ when x"C" => reg(12) <= I_DA;
+ when x"D" => reg(13) <= I_DA;
+ when x"E" => reg(14) <= I_DA;
+ when x"F" => reg(15) <= I_DA;
+ when others => null;
+ end case;
+ end if;
+
+ env_reset <= '0';
+ if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then
+ env_reset <= '1';
+ end if;
+ end process;
+
+ p_rdata : process(busctrl_re, addr, reg)
+ begin
+ O_DA <= (others => '0'); -- 'X'
+ if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
+ case addr(3 downto 0) is
+ when x"0" => O_DA <= reg(0) ;
+ when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
+ when x"2" => O_DA <= reg(2) ;
+ when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
+ when x"4" => O_DA <= reg(4) ;
+ when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
+ when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ;
+ when x"7" => O_DA <= reg(7) ;
+ when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ;
+ when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ;
+ when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ;
+ when x"B" => O_DA <= reg(11);
+ when x"C" => O_DA <= reg(12);
+ when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
+ when x"E" => if (reg(7)(6) = '0') then -- input
+ O_DA <= ioa_inreg;
+ else
+ O_DA <= reg(14); -- read output reg
+ end if;
+ when x"F" => if (Reg(7)(7) = '0') then
+ O_DA <= iob_inreg;
+ else
+ O_DA <= reg(15);
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end process;
+ --
+ p_divider : process
+ begin
+ wait until rising_edge(CLK);
+ -- / 8 when SEL is high and /16 when SEL is low
+ if (ENA = '1') then
+ ena_div <= '0';
+ ena_div_noise <= '0';
+ if (cnt_div = "0000") then
+ cnt_div <= (not I_SEL_L) & "111";
+ ena_div <= '1';
+
+ noise_div <= not noise_div;
+ if (noise_div = '1') then
+ ena_div_noise <= '1';
+ end if;
+ else
+ cnt_div <= cnt_div - "1";
+ end if;
+ end if;
+ end process;
+
+ p_noise_gen : process
+ variable noise_gen_comp : std_logic_vector(4 downto 0);
+ variable poly17_zero : std_logic;
+ begin
+ wait until rising_edge(CLK);
+
+ if (reg(6)(4 downto 0) = "00000") then
+ noise_gen_comp := "00000";
+ else
+ noise_gen_comp := (reg(6)(4 downto 0) - "1");
+ end if;
+
+ poly17_zero := '0';
+ if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
+
+ if (ENA = '1') then
+
+ if (ena_div_noise = '1') then -- divider ena
+
+ if (noise_gen_cnt >= noise_gen_comp) then
+ noise_gen_cnt <= "00000";
+ poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
+ else
+ noise_gen_cnt <= (noise_gen_cnt + "1");
+ end if;
+ end if;
+ end if;
+ end process;
+ noise_gen_op <= poly17(0);
+
+ p_tone_gens : process
+ variable tone_gen_freq : array_3x12;
+ variable tone_gen_comp : array_3x12;
+ begin
+ wait until rising_edge(CLK);
+
+ -- looks like real chips count up - we need to get the Exact behaviour ..
+ tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
+ tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
+ tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
+ -- period 0 = period 1
+ for i in 1 to 3 loop
+ if (tone_gen_freq(i) = x"000") then
+ tone_gen_comp(i) := x"000";
+ else
+ tone_gen_comp(i) := (tone_gen_freq(i) - "1");
+ end if;
+ end loop;
+
+ if (ENA = '1') then
+ for i in 1 to 3 loop
+ if (ena_div = '1') then -- divider ena
+
+ if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
+ tone_gen_cnt(i) <= x"000";
+ tone_gen_op(i) <= not tone_gen_op(i);
+ else
+ tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
+ end if;
+ end if;
+ end loop;
+ end if;
+ end process;
+
+ p_envelope_freq : process
+ variable env_gen_freq : std_logic_vector(15 downto 0);
+ variable env_gen_comp : std_logic_vector(15 downto 0);
+ begin
+ wait until rising_edge(CLK);
+ env_gen_freq := reg(12) & reg(11);
+ -- envelope freqs 1 and 0 are the same.
+ if (env_gen_freq = x"0000") then
+ env_gen_comp := x"0000";
+ else
+ env_gen_comp := (env_gen_freq - "1");
+ end if;
+
+ if (ENA = '1') then
+ env_ena <= '0';
+ if (ena_div = '1') then -- divider ena
+ if (env_gen_cnt >= env_gen_comp) then
+ env_gen_cnt <= x"0000";
+ env_ena <= '1';
+ else
+ env_gen_cnt <= (env_gen_cnt + "1");
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_envelope_shape : process(env_reset, CLK)
+ variable is_bot : boolean;
+ variable is_bot_p1 : boolean;
+ variable is_top_m1 : boolean;
+ variable is_top : boolean;
+ begin
+ -- envelope shapes
+ -- C AtAlH
+ -- 0 0 x x \___
+ --
+ -- 0 1 x x /___
+ --
+ -- 1 0 0 0 \\\\
+ --
+ -- 1 0 0 1 \___
+ --
+ -- 1 0 1 0 \/\/
+ -- ___
+ -- 1 0 1 1 \
+ --
+ -- 1 1 0 0 ////
+ -- ___
+ -- 1 1 0 1 /
+ --
+ -- 1 1 1 0 /\/\
+ --
+ -- 1 1 1 1 /___
+ if (env_reset = '1') then
+ -- load initial state
+ if (reg(13)(2) = '0') then -- attack
+ env_vol <= "11111";
+ env_inc <= '0'; -- -1
+ else
+ env_vol <= "00000";
+ env_inc <= '1'; -- +1
+ end if;
+ env_hold <= '0';
+
+ elsif rising_edge(CLK) then
+ is_bot := (env_vol = "00000");
+ is_bot_p1 := (env_vol = "00001");
+ is_top_m1 := (env_vol = "11110");
+ is_top := (env_vol = "11111");
+
+ if (ENA = '1') then
+ if (env_ena = '1') then
+ if (env_hold = '0') then
+ if (env_inc = '1') then
+ env_vol <= (env_vol + "00001");
+ else
+ env_vol <= (env_vol + "11111");
+ end if;
+ end if;
+
+ -- envelope shape control.
+ if (reg(13)(3) = '0') then
+ if (env_inc = '0') then -- down
+ if is_bot_p1 then env_hold <= '1'; end if;
+ else
+ if is_top then env_hold <= '1'; end if;
+ end if;
+ else
+ if (reg(13)(0) = '1') then -- hold = 1
+ if (env_inc = '0') then -- down
+ if (reg(13)(1) = '1') then -- alt
+ if is_bot then env_hold <= '1'; end if;
+ else
+ if is_bot_p1 then env_hold <= '1'; end if;
+ end if;
+ else
+ if (reg(13)(1) = '1') then -- alt
+ if is_top then env_hold <= '1'; end if;
+ else
+ if is_top_m1 then env_hold <= '1'; end if;
+ end if;
+ end if;
+
+ elsif (reg(13)(1) = '1') then -- alternate
+ if (env_inc = '0') then -- down
+ if is_bot_p1 then env_hold <= '1'; end if;
+ if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
+ else
+ if is_top_m1 then env_hold <= '1'; end if;
+ if is_top then env_hold <= '0'; env_inc <= '0'; end if;
+ end if;
+ end if;
+
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_chan_mixer : process(cnt_div, reg, tone_gen_op)
+ begin
+ tone_ena_l <= '1'; tone_src <= '1';
+ noise_ena_l <= '1'; chan_vol <= "00000";
+ case cnt_div(1 downto 0) is
+ when "00" =>
+ tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0);
+ noise_ena_l <= reg(7)(3);
+ when "01" =>
+ tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0);
+ noise_ena_l <= reg(7)(4);
+ when "10" =>
+ tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
+ noise_ena_l <= reg(7)(5);
+ when "11" => null; -- tone gen outputs become valid on this clock
+ when others => null;
+ end case;
+ end process;
+
+ p_op_mixer : process
+ variable chan_mixed : std_logic;
+ variable chan_amp : std_logic_vector(4 downto 0);
+ begin
+ wait until rising_edge(CLK);
+ if (ENA = '1') then
+
+ chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
+
+ chan_amp := (others => '0');
+ if (chan_mixed = '1') then
+ if (chan_vol(4) = '0') then
+ if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
+ chan_amp := "00000";
+ else
+ chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
+ end if;
+ else
+ chan_amp := env_vol(4 downto 0);
+ end if;
+ end if;
+
+ dac_amp <= x"00";
+ case chan_amp is
+ when "11111" => dac_amp <= x"FF";
+ when "11110" => dac_amp <= x"D9";
+ when "11101" => dac_amp <= x"BA";
+ when "11100" => dac_amp <= x"9F";
+ when "11011" => dac_amp <= x"88";
+ when "11010" => dac_amp <= x"74";
+ when "11001" => dac_amp <= x"63";
+ when "11000" => dac_amp <= x"54";
+ when "10111" => dac_amp <= x"48";
+ when "10110" => dac_amp <= x"3D";
+ when "10101" => dac_amp <= x"34";
+ when "10100" => dac_amp <= x"2C";
+ when "10011" => dac_amp <= x"25";
+ when "10010" => dac_amp <= x"1F";
+ when "10001" => dac_amp <= x"1A";
+ when "10000" => dac_amp <= x"16";
+ when "01111" => dac_amp <= x"13";
+ when "01110" => dac_amp <= x"10";
+ when "01101" => dac_amp <= x"0D";
+ when "01100" => dac_amp <= x"0B";
+ when "01011" => dac_amp <= x"09";
+ when "01010" => dac_amp <= x"08";
+ when "01001" => dac_amp <= x"07";
+ when "01000" => dac_amp <= x"06";
+ when "00111" => dac_amp <= x"05";
+ when "00110" => dac_amp <= x"04";
+ when "00101" => dac_amp <= x"03";
+ when "00100" => dac_amp <= x"03";
+ when "00011" => dac_amp <= x"02";
+ when "00010" => dac_amp <= x"02";
+ when "00001" => dac_amp <= x"01";
+ when "00000" => dac_amp <= x"00";
+ when others => null;
+ end case;
+
+ if (cnt_div(1 downto 0) = "10") then
+ audio_mix <= (others => '0');
+ audio_final <= audio_mix;
+ else
+ audio_mix <= audio_mix + ("00" & dac_amp);
+ end if;
+
+ if (RESET_L = '0') then
+ O_AUDIO(7 downto 0) <= "00000000";
+ else
+ if (audio_final(9) = '0') then
+ O_AUDIO(7 downto 0) <= audio_final(8 downto 1);
+ else -- clip
+ O_AUDIO(7 downto 0) <= x"FF";
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_io_ports : process(reg)
+ begin
+ O_IOA <= reg(14);
+
+ O_IOA_OE_L <= not reg(7)(6);
+ O_IOB <= reg(15);
+ O_IOB_OE_L <= not reg(7)(7);
+ end process;
+
+ p_io_ports_inreg : process
+ begin
+ wait until rising_edge(CLK);
+ ioa_inreg <= I_IOA;
+ iob_inreg <= I_IOB;
+ end process;
+end architecture RTL;
diff --git a/ym2149/YM2149_tb.vhd b/ym2149/YM2149_tb.vhd
new file mode 100644
index 0000000..4a29564
--- /dev/null
+++ b/ym2149/YM2149_tb.vhd
@@ -0,0 +1,212 @@
+
+use std.textio.ALL;
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
+
+entity YM2149_TB is
+end;
+
+architecture Sim of YM2149_TB is
+ component YM2149
+ port (
+ -- data bus
+ I_DA : in std_logic_vector(7 downto 0);
+ O_DA : out std_logic_vector(7 downto 0);
+ O_DA_OE_L : out std_logic;
+ -- control
+ I_A9_L : in std_logic;
+ I_A8 : in std_logic;
+ I_BDIR : in std_logic;
+ I_BC2 : in std_logic;
+ I_BC1 : in std_logic;
+ I_SEL_L : in std_logic;
+
+ O_AUDIO : out std_logic_vector(7 downto 0);
+ -- port a
+ I_IOA : in std_logic_vector(7 downto 0);
+ O_IOA : out std_logic_vector(7 downto 0);
+ O_IOA_OE_L : out std_logic;
+ -- port b
+ I_IOB : in std_logic_vector(7 downto 0);
+ O_IOB : out std_logic_vector(7 downto 0);
+ O_IOB_OE_L : out std_logic;
+
+ ENA : in std_logic; -- clock enable for higher speed operation
+ RESET_L : in std_logic;
+ CLK : in std_logic -- note 6 Mhz
+ );
+ end component;
+
+ -- signals
+ constant CLKPERIOD : time := 25 ns;
+ signal func : string(8 downto 1);
+
+ signal clk : std_logic;
+ signal reset_l : std_logic;
+ signal reset_h : std_logic;
+
+ signal da_in : std_logic_vector(7 downto 0);
+ signal da_out : std_logic_vector(7 downto 0);
+ signal da_oe_l : std_logic;
+ signal bdir : std_logic;
+ signal bc2 : std_logic;
+ signal bc1 : std_logic;
+ signal audio : std_logic_vector(7 downto 0);
+ signal ioa_in : std_logic_vector(7 downto 0);
+ signal ioa_out : std_logic_vector(7 downto 0);
+ signal ioa_oe_l : std_logic;
+ signal iob_in : std_logic_vector(7 downto 0);
+ signal iob_out : std_logic_vector(7 downto 0);
+ signal iob_oe_l : std_logic;
+begin
+ u0 : YM2149
+ port map (
+ -- data bus
+ I_DA => da_in,
+ O_DA => da_out,
+ O_DA_OE_L => da_oe_l,
+ -- control
+ I_A9_L => '0',
+ I_A8 => '1',
+ I_BDIR => bdir,
+ I_BC2 => bc2,
+ I_BC1 => bc1,
+ I_SEL_L => '1',
+
+ O_AUDIO => audio,
+ -- port a
+ I_IOA => ioa_in,
+ O_IOA => ioa_out,
+ O_IOA_OE_L => ioa_oe_l,
+ -- port b
+ I_IOB => iob_in,
+ O_IOB => iob_out,
+ O_IOB_OE_L => iob_oe_l,
+
+ ENA => '1',
+ RESET_L => reset_l,
+ CLK => clk
+ );
+
+ p_clk : process
+ begin
+ CLK <= '0';
+ wait for CLKPERIOD / 2;
+ CLK <= '1';
+ wait for CLKPERIOD - (CLKPERIOD / 2);
+ end process;
+
+ p_debug_comb : process(bdir, bc2, bc1)
+ variable sel : std_logic_vector(2 downto 0);
+ begin
+ func <= "-XXXXXX-";
+ sel := bdir & bc2 & bc1;
+ case sel is
+ when "000" |
+ "010" |
+ "101" => func <= "inactive";
+ when "001" |
+ "100" |
+ "111" => func <= "address ";
+ when "011" => func <= "read ";
+ when "110" => func <= "write ";
+ when others => null;
+ end case;
+ end process;
+
+ p_test : process
+
+ procedure write(
+ addr : in bit_vector(3 downto 0);
+ data : in bit_vector(7 downto 0)
+ ) is
+ begin
+ wait until rising_edge(clk);
+ -- addr
+ bdir <= '1';
+ bc2 <= '1';
+ bc1 <= '1';
+ da_in <= x"0" & to_stdlogicvector(addr);
+ wait for 300 ns;
+ bdir <= '0';
+ bc2 <= '0';
+ bc1 <= '0';
+ wait for 80 ns;
+ da_in <= (others => 'Z');
+ wait for 100 ns;
+ -- write
+ bdir <= '1';
+ bc2 <= '1';
+ bc1 <= '0';
+ da_in <= to_stdlogicvector(data);
+ wait for 300 ns;
+ bdir <= '0';
+ bc2 <= '0';
+ bc1 <= '0';
+ wait for 80 ns;
+ da_in <= (others => 'Z');
+ wait for 100 ns;
+ wait until rising_edge(clk);
+
+ end write;
+
+ procedure read(
+ addr : in bit_vector(3 downto 0)
+ ) is
+ begin
+ wait until rising_edge(clk);
+ -- addr
+ bdir <= '1';
+ bc2 <= '1';
+ bc1 <= '1';
+ da_in <= x"0" & to_stdlogicvector(addr);
+ wait for 300 ns;
+ bdir <= '0';
+ bc2 <= '0';
+ bc1 <= '0';
+ wait for 80 ns;
+ da_in <= (others => 'Z');
+ wait for 100 ns;
+ -- read
+ bdir <= '0';
+ bc2 <= '1';
+ bc1 <= '1';
+ da_in <= (others => 'Z');
+ wait for 300 ns;
+ bdir <= '0';
+ bc2 <= '0';
+ bc1 <= '0';
+ wait for 180 ns;
+ wait until rising_edge(clk);
+
+ end read;
+
+ begin
+ reset_l <= '0';
+ reset_h <= '1';
+ da_in <= (others => 'Z');
+ bdir <= '0';
+ bc2 <= '0';
+ bc1 <= '0';
+ wait for 100 ns;
+ reset_l <= '1';
+ reset_h <= '0';
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ wait until rising_edge(clk);
+ write(x"0",x"08");
+ write(x"1",x"00");
+ read(x"0");
+ wait for 500 ns;
+ write(x"7",x"fb");
+ write(x"8",x"00");
+ write(x"a",x"0f");
+ write(x"B",x"00");
+ write(x"C",x"00");
+ write(x"D",x"0E");
+ wait;
+ end process;
+
+end Sim;
diff --git a/ym2149/YM2149_volmix.vhd b/ym2149/YM2149_volmix.vhd
new file mode 100644
index 0000000..7afcfb1
--- /dev/null
+++ b/ym2149/YM2149_volmix.vhd
@@ -0,0 +1,583 @@
+--
+-- A simulation model of YM2149 (AY-3-8910 with bells on)
+
+-- Copyright (c) MikeJ - Jan 2005
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.fpgaarcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- Revision list
+--
+-- version 001 initial release
+--
+-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
+--
+-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
+-- vol 15 .. 0
+-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
+-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
+-- to produced all the required values.
+-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
+--
+-- NOTE, this component uses a volume table for accurate mixing of the three analogue channels,
+-- where the outputs are wired together - like in the Atari ST
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.std_logic_arith.all;
+ use ieee.std_logic_unsigned.all;
+
+entity YM2149 is
+ port (
+ -- data bus
+ I_DA : in std_logic_vector(7 downto 0);
+ O_DA : out std_logic_vector(7 downto 0);
+ O_DA_OE_L : out std_logic;
+ -- control
+ I_A9_L : in std_logic;
+ I_A8 : in std_logic;
+ I_BDIR : in std_logic;
+ I_BC2 : in std_logic;
+ I_BC1 : in std_logic;
+ I_SEL_L : in std_logic;
+
+ O_AUDIO : out std_logic_vector(7 downto 0);
+ -- port a
+ I_IOA : in std_logic_vector(7 downto 0);
+ O_IOA : out std_logic_vector(7 downto 0);
+ O_IOA_OE_L : out std_logic;
+ -- port b
+ I_IOB : in std_logic_vector(7 downto 0);
+ O_IOB : out std_logic_vector(7 downto 0);
+ O_IOB_OE_L : out std_logic;
+ --
+ ENA : in std_logic; -- clock enable for higher speed operation
+ RESET_L : in std_logic;
+ CLK : in std_logic -- note 6 Mhz
+ );
+end;
+
+architecture RTL of YM2149 is
+
+ component vol_table
+ port (
+ CLK : in std_logic;
+ ADDR : in std_logic_vector(11 downto 0);
+ DATA : out std_logic_vector(9 downto 0)
+ );
+ end component;
+
+ -- signals
+ type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0);
+ type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
+
+ signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
+ signal noise_div : std_logic := '0';
+ signal ena_div : std_logic;
+ signal ena_div_noise : std_logic;
+ signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
+
+ -- registers
+ signal addr : std_logic_vector(7 downto 0);
+ signal busctrl_addr : std_logic;
+ signal busctrl_we : std_logic;
+ signal busctrl_re : std_logic;
+
+ signal reg : array_16x8;
+ signal env_reset : std_logic;
+ signal ioa_inreg : std_logic_vector(7 downto 0);
+ signal iob_inreg : std_logic_vector(7 downto 0);
+
+ signal noise_gen_cnt : std_logic_vector(4 downto 0);
+ signal noise_gen_op : std_logic;
+ signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
+ signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
+
+ signal env_gen_cnt : std_logic_vector(15 downto 0);
+ signal env_ena : std_logic;
+ signal env_hold : std_logic;
+ signal env_inc : std_logic;
+ signal env_vol : std_logic_vector(4 downto 0);
+
+ signal vol_table_in : std_logic_vector(11 downto 0);
+ signal vol_table_out : std_logic_vector(9 downto 0);
+
+begin
+ -- cpu i/f
+ p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
+ variable cs : std_logic;
+ variable sel : std_logic_vector(2 downto 0);
+ begin
+ -- BDIR BC2 BC1 MODE
+ -- 0 0 0 inactive
+ -- 0 0 1 address
+ -- 0 1 0 inactive
+ -- 0 1 1 read
+ -- 1 0 0 address
+ -- 1 0 1 inactive
+ -- 1 1 0 write
+ -- 1 1 1 read
+ busctrl_addr <= '0';
+ busctrl_we <= '0';
+ busctrl_re <= '0';
+
+ cs := '0';
+ if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
+ cs := '1';
+ end if;
+
+ sel := (I_BDIR & I_BC2 & I_BC1);
+ case sel is
+ when "000" => null;
+ when "001" => busctrl_addr <= '1';
+ when "010" => null;
+ when "011" => busctrl_re <= cs;
+ when "100" => busctrl_addr <= '1';
+ when "101" => null;
+ when "110" => busctrl_we <= cs;
+ when "111" => busctrl_addr <= '1';
+ when others => null;
+ end case;
+ end process;
+
+ p_oe : process(busctrl_re)
+ begin
+ -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
+ O_DA_OE_L <= not (busctrl_re);
+ end process;
+
+ -- CLOCKED
+ --p_waddr : process
+ --begin
+ ---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+ --wait until rising_edge(CLK);
+
+ --if (RESET_L = '0') then
+ --addr <= (others => '0');
+ --else
+ --if (busctrl_addr = '1') then
+ --addr <= I_DA;
+ --end if;
+ --end if;
+ --end process;
+ --p_wdata : process
+ --begin
+ ---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+ --wait until rising_edge(CLK);
+ --env_reset <= '0';
+
+ --if (RESET_L = '0') then
+ --reg <= (others => (others => '0'));
+ --env_reset <= '1';
+ --else
+ --env_reset <= '0';
+ --if (busctrl_we = '1') then
+ --case addr(3 downto 0) is
+ --when x"0" => reg(0) <= I_DA;
+ --when x"1" => reg(1) <= I_DA;
+ --when x"2" => reg(2) <= I_DA;
+ --when x"3" => reg(3) <= I_DA;
+ --when x"4" => reg(4) <= I_DA;
+ --when x"5" => reg(5) <= I_DA;
+ --when x"6" => reg(6) <= I_DA;
+ --when x"7" => reg(7) <= I_DA;
+ --when x"8" => reg(8) <= I_DA;
+ --when x"9" => reg(9) <= I_DA;
+ --when x"A" => reg(10) <= I_DA;
+ --when x"B" => reg(11) <= I_DA;
+ --when x"C" => reg(12) <= I_DA;
+ --when x"D" => reg(13) <= I_DA; env_reset <= '1';
+ --when x"E" => reg(14) <= I_DA;
+ --when x"F" => reg(15) <= I_DA;
+ --when others => null;
+ --end case;
+ --end if;
+ --end if;
+ --end process;
+
+ -- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock.
+ p_waddr : process(reset_l, busctrl_addr)
+ begin
+ -- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+ if (RESET_L = '0') then
+ addr <= (others => '0');
+ elsif falling_edge(busctrl_addr) then -- yuk
+ addr <= I_DA;
+ end if;
+ end process;
+
+ p_wdata : process(reset_l, busctrl_we, addr)
+ begin
+ if (RESET_L = '0') then
+ reg <= (others => (others => '0'));
+ elsif falling_edge(busctrl_we) then
+ case addr(3 downto 0) is
+ when x"0" => reg(0) <= I_DA;
+ when x"1" => reg(1) <= I_DA;
+ when x"2" => reg(2) <= I_DA;
+ when x"3" => reg(3) <= I_DA;
+ when x"4" => reg(4) <= I_DA;
+ when x"5" => reg(5) <= I_DA;
+ when x"6" => reg(6) <= I_DA;
+ when x"7" => reg(7) <= I_DA;
+ when x"8" => reg(8) <= I_DA;
+ when x"9" => reg(9) <= I_DA;
+ when x"A" => reg(10) <= I_DA;
+ when x"B" => reg(11) <= I_DA;
+ when x"C" => reg(12) <= I_DA;
+ when x"D" => reg(13) <= I_DA;
+ when x"E" => reg(14) <= I_DA;
+ when x"F" => reg(15) <= I_DA;
+ when others => null;
+ end case;
+ end if;
+
+ env_reset <= '0';
+ if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then
+ env_reset <= '1';
+ end if;
+ end process;
+
+ p_rdata : process(busctrl_re, addr, reg)
+ begin
+ O_DA <= (others => '0'); -- 'X'
+ if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
+ case addr(3 downto 0) is
+ when x"0" => O_DA <= reg(0) ;
+ when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
+ when x"2" => O_DA <= reg(2) ;
+ when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
+ when x"4" => O_DA <= reg(4) ;
+ when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
+ when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ;
+ when x"7" => O_DA <= reg(7) ;
+ when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ;
+ when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ;
+ when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ;
+ when x"B" => O_DA <= reg(11);
+ when x"C" => O_DA <= reg(12);
+ when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
+ when x"E" => if (reg(7)(6) = '0') then -- input
+ O_DA <= ioa_inreg;
+ else
+ O_DA <= reg(14); -- read output reg
+ end if;
+ when x"F" => if (Reg(7)(7) = '0') then
+ O_DA <= iob_inreg;
+ else
+ O_DA <= reg(15);
+ end if;
+ when others => null;
+ end case;
+ end if;
+ end process;
+ --
+ p_divider : process
+ begin
+ wait until rising_edge(CLK);
+ -- / 8 when SEL is high and /16 when SEL is low
+ if (ENA = '1') then
+ ena_div <= '0';
+ ena_div_noise <= '0';
+ if (cnt_div = "0000") then
+ cnt_div <= (not I_SEL_L) & "111";
+ ena_div <= '1';
+
+ noise_div <= not noise_div;
+ if (noise_div = '1') then
+ ena_div_noise <= '1';
+ end if;
+ else
+ cnt_div <= cnt_div - "1";
+ end if;
+ end if;
+ end process;
+
+ p_noise_gen : process
+ variable noise_gen_comp : std_logic_vector(4 downto 0);
+ variable poly17_zero : std_logic;
+ begin
+ wait until rising_edge(CLK);
+
+ if (reg(6)(4 downto 0) = "00000") then
+ noise_gen_comp := "00000";
+ else
+ noise_gen_comp := (reg(6)(4 downto 0) - "1");
+ end if;
+
+ poly17_zero := '0';
+ if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
+
+ if (ENA = '1') then
+
+ if (ena_div_noise = '1') then -- divider ena
+
+ if (noise_gen_cnt >= noise_gen_comp) then
+ noise_gen_cnt <= "00000";
+ poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
+ else
+ noise_gen_cnt <= (noise_gen_cnt + "1");
+ end if;
+ end if;
+ end if;
+ end process;
+ noise_gen_op <= poly17(0);
+
+ p_tone_gens : process
+ variable tone_gen_freq : array_3x12;
+ variable tone_gen_comp : array_3x12;
+ begin
+ wait until rising_edge(CLK);
+
+ -- looks like real chips count up - we need to get the Exact behaviour ..
+ tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
+ tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
+ tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
+ -- period 0 = period 1
+ for i in 1 to 3 loop
+ if (tone_gen_freq(i) = x"000") then
+ tone_gen_comp(i) := x"000";
+ else
+ tone_gen_comp(i) := (tone_gen_freq(i) - "1");
+ end if;
+ end loop;
+
+ if (ENA = '1') then
+ for i in 1 to 3 loop
+ if (ena_div = '1') then -- divider ena
+
+ if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
+ tone_gen_cnt(i) <= x"000";
+ tone_gen_op(i) <= not tone_gen_op(i);
+ else
+ tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
+ end if;
+ end if;
+ end loop;
+ end if;
+ end process;
+
+ p_envelope_freq : process
+ variable env_gen_freq : std_logic_vector(15 downto 0);
+ variable env_gen_comp : std_logic_vector(15 downto 0);
+ begin
+ wait until rising_edge(CLK);
+ env_gen_freq := reg(12) & reg(11);
+ -- envelope freqs 1 and 0 are the same.
+ if (env_gen_freq = x"0000") then
+ env_gen_comp := x"0000";
+ else
+ env_gen_comp := (env_gen_freq - "1");
+ end if;
+
+ if (ENA = '1') then
+ env_ena <= '0';
+ if (ena_div = '1') then -- divider ena
+ if (env_gen_cnt >= env_gen_comp) then
+ env_gen_cnt <= x"0000";
+ env_ena <= '1';
+ else
+ env_gen_cnt <= (env_gen_cnt + "1");
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_envelope_shape : process(env_reset, CLK)
+ variable is_bot : boolean;
+ variable is_bot_p1 : boolean;
+ variable is_top_m1 : boolean;
+ variable is_top : boolean;
+ begin
+ -- envelope shapes
+ -- C AtAlH
+ -- 0 0 x x \___
+ --
+ -- 0 1 x x /___
+ --
+ -- 1 0 0 0 \\\\
+ --
+ -- 1 0 0 1 \___
+ --
+ -- 1 0 1 0 \/\/
+ -- ___
+ -- 1 0 1 1 \
+ --
+ -- 1 1 0 0 ////
+ -- ___
+ -- 1 1 0 1 /
+ --
+ -- 1 1 1 0 /\/\
+ --
+ -- 1 1 1 1 /___
+ if (env_reset = '1') then
+ -- load initial state
+ if (reg(13)(2) = '0') then -- attack
+ env_vol <= "11111";
+ env_inc <= '0'; -- -1
+ else
+ env_vol <= "00000";
+ env_inc <= '1'; -- +1
+ end if;
+ env_hold <= '0';
+
+ elsif rising_edge(CLK) then
+ is_bot := (env_vol = "00000");
+ is_bot_p1 := (env_vol = "00001");
+ is_top_m1 := (env_vol = "11110");
+ is_top := (env_vol = "11111");
+
+ if (ENA = '1') then
+ if (env_ena = '1') then
+ if (env_hold = '0') then
+ if (env_inc = '1') then
+ env_vol <= (env_vol + "00001");
+ else
+ env_vol <= (env_vol + "11111");
+ end if;
+ end if;
+
+ -- envelope shape control.
+ if (reg(13)(3) = '0') then
+ if (env_inc = '0') then -- down
+ if is_bot_p1 then env_hold <= '1'; end if;
+ else
+ if is_top then env_hold <= '1'; end if;
+ end if;
+ else
+ if (reg(13)(0) = '1') then -- hold = 1
+ if (env_inc = '0') then -- down
+ if (reg(13)(1) = '1') then -- alt
+ if is_bot then env_hold <= '1'; end if;
+ else
+ if is_bot_p1 then env_hold <= '1'; end if;
+ end if;
+ else
+ if (reg(13)(1) = '1') then -- alt
+ if is_top then env_hold <= '1'; end if;
+ else
+ if is_top_m1 then env_hold <= '1'; end if;
+ end if;
+ end if;
+
+ elsif (reg(13)(1) = '1') then -- alternate
+ if (env_inc = '0') then -- down
+ if is_bot_p1 then env_hold <= '1'; end if;
+ if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
+ else
+ if is_top_m1 then env_hold <= '1'; end if;
+ if is_top then env_hold <= '0'; env_inc <= '0'; end if;
+ end if;
+ end if;
+
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_chan_mixer_table : process
+ variable chan_mixed : std_logic_vector(2 downto 0);
+ begin
+ wait until rising_edge(CLK);
+ if (ENA = '1') then
+ chan_mixed(0) := (reg(7)(0) or tone_gen_op(1)) and (reg(7)(3) or noise_gen_op);
+ chan_mixed(1) := (reg(7)(1) or tone_gen_op(2)) and (reg(7)(4) or noise_gen_op);
+ chan_mixed(2) := (reg(7)(2) or tone_gen_op(3)) and (reg(7)(5) or noise_gen_op);
+
+ vol_table_in <= x"000";
+
+ if (chan_mixed(0) = '1') then
+ if (reg(8)(4) = '0') then
+ vol_table_in(3 downto 0) <= reg(8)(3 downto 0);
+ else
+ vol_table_in(3 downto 0) <= env_vol(4 downto 1);
+ end if;
+ end if;
+
+ if (chan_mixed(1) = '1') then
+ if (reg(9)(4) = '0') then
+ vol_table_in(7 downto 4) <= reg(9)(3 downto 0);
+ else
+ vol_table_in(7 downto 4) <= env_vol(4 downto 1);
+ end if;
+ end if;
+
+ if (chan_mixed(2) = '1') then
+ if (reg(10)(4) = '0') then
+ vol_table_in(11 downto 8) <= reg(10)(3 downto 0);
+ else
+ vol_table_in(11 downto 8) <= env_vol(4 downto 1);
+ end if;
+ end if;
+ end if;
+ end process;
+
+ u_vol_table : vol_table
+ port map (
+ CLK => clk,
+ ADDR => vol_table_in,
+ DATA => vol_table_out
+ );
+
+ p_op_mixer : process
+ variable chan_mixed : std_logic;
+ variable chan_amp : std_logic_vector(4 downto 0);
+ begin
+ wait until rising_edge(CLK);
+
+ if (RESET_L = '0') then
+ O_AUDIO(7 downto 0) <= "00000000";
+ else
+ O_AUDIO(7 downto 0) <= vol_table_out(9 downto 2);
+ end if;
+ end process;
+
+ p_io_ports : process(reg)
+ begin
+ -- input low
+ O_IOA <= reg(14);
+
+ O_IOA_OE_L <= not reg(7)(6);
+ O_IOB <= reg(15);
+ O_IOB_OE_L <= not reg(7)(7);
+ end process;
+
+ p_io_ports_inreg : process
+ begin
+ wait until rising_edge(CLK);
+ ioa_inreg <= I_IOA;
+ iob_inreg <= I_IOB;
+ end process;
+end architecture RTL;
diff --git a/ym2149/vol_table.vhd b/ym2149/vol_table.vhd
new file mode 100644
index 0000000..aab84ba
--- /dev/null
+++ b/ym2149/vol_table.vhd
@@ -0,0 +1,592 @@
+-- generated with tablegen by MikeJ
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vol_table is
+ port (
+ CLK : in std_logic;
+ ADDR : in std_logic_vector(11 downto 0);
+ DATA : out std_logic_vector(9 downto 0)
+ );
+end;
+
+architecture RTL of vol_table is
+
+ function romgen_str2slv (str : string) return std_logic_vector is
+ variable result : std_logic_vector (str'length*4-1 downto 0);
+ begin
+ for i in 0 to str'length-1 loop
+ case str(str'high-i) is
+ when '0' => result(i*4+3 downto i*4) := x"0";
+ when '1' => result(i*4+3 downto i*4) := x"1";
+ when '2' => result(i*4+3 downto i*4) := x"2";
+ when '3' => result(i*4+3 downto i*4) := x"3";
+ when '4' => result(i*4+3 downto i*4) := x"4";
+ when '5' => result(i*4+3 downto i*4) := x"5";
+ when '6' => result(i*4+3 downto i*4) := x"6";
+ when '7' => result(i*4+3 downto i*4) := x"7";
+ when '8' => result(i*4+3 downto i*4) := x"8";
+ when '9' => result(i*4+3 downto i*4) := x"9";
+ when 'A' => result(i*4+3 downto i*4) := x"A";
+ when 'B' => result(i*4+3 downto i*4) := x"B";
+ when 'C' => result(i*4+3 downto i*4) := x"C";
+ when 'D' => result(i*4+3 downto i*4) := x"D";
+ when 'E' => result(i*4+3 downto i*4) := x"E";
+ when 'F' => result(i*4+3 downto i*4) := x"F";
+ when others => result(i*4+3 downto i*4) := "XXXX";
+ end case;
+ end loop;
+ return result;
+ end romgen_str2slv;
+
+ attribute INIT_00 : string;
+ attribute INIT_01 : string;
+ attribute INIT_02 : string;
+ attribute INIT_03 : string;
+ attribute INIT_04 : string;
+ attribute INIT_05 : string;
+ attribute INIT_06 : string;
+ attribute INIT_07 : string;
+ attribute INIT_08 : string;
+ attribute INIT_09 : string;
+ attribute INIT_0A : string;
+ attribute INIT_0B : string;
+ attribute INIT_0C : string;
+ attribute INIT_0D : string;
+ attribute INIT_0E : string;
+ attribute INIT_0F : string;
+
+ component RAMB4_S1
+ --pragma translate_off
+ generic (
+ INIT_00 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_01 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_02 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_03 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_04 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_05 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_06 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_07 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_08 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_09 : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_0A : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_0B : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_0C : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_0D : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_0E : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000";
+ INIT_0F : std_logic_vector (255 downto 0) := x"0000000000000000000000000000000000000000000000000000000000000000"
+ );
+ --pragma translate_on
+ port (
+ DO : out std_logic_vector (0 downto 0);
+ DI : in std_logic_vector (0 downto 0);
+ ADDR : in std_logic_vector (11 downto 0);
+ WE : in std_logic;
+ EN : in std_logic;
+ RST : in std_logic;
+ CLK : in std_logic
+ );
+ end component;
+
+ signal rom_addr : std_logic_vector(11 downto 0);
+
+begin
+
+ p_addr : process(ADDR)
+ begin
+ rom_addr <= (others => '0');
+ rom_addr(11 downto 0) <= ADDR;
+ end process;
+
+ rom0 : if true generate
+ attribute INIT_00 of inst : label is "A3FF3C09E03755DF43AF510A88509D3598CB92F0A961B34BDC9EB90EBC9EF9B0";
+ attribute INIT_01 of inst : label is "D800C6FA0A6395DFAAAF531A6C54157058DB73B4696057CE5C971A5E7C9F388A";
+ attribute INIT_02 of inst : label is "6000F915F5986A225C1A2F6F9791E7BDA38FA4709571EB63AD8EC58E9C9EC7B0";
+ attribute INIT_03 of inst : label is "1C00040D089C9222A41A4F6F179107B5238B047415602B4A6C97654E1C9F478A";
+ attribute INIT_04 of inst : label is "EFFFF40DE8C91B07B42FCB10946EB44AA074A38B8A9F84B5EB68DAB19B60F875";
+ attribute INIT_05 of inst : label is "0FFF65D647760C68995AF46E23D44B7042F05F8F359F6BB51C6866716C600075";
+ attribute INIT_06 of inst : label is "C800CD56163C1C07D4247FF7249045B027F0448F0D9F67B520687C7254641470";
+ attribute INIT_07 of inst : label is "B4007DFAD1438123C92447EF04947DEB47EE65F07DD0626A45972E8D759B150F";
+ attribute INIT_08 of inst : label is "4000A1A97389B7E38F201AD0BD60DAB2F5F7B690DBA085CEC0118091B190F08D";
+ attribute INIT_09 of inst : label is "3C0036FBD8C6C6582120D59571170ECC45107108681076AE715127114210460C";
+ attribute INIT_0A of inst : label is "9400428534F9414305C03FDEE7E0BF0CCE379E1782AF84D2852FE5EDB4F8D0EC";
+ attribute INIT_0B of inst : label is "13FF36867E392B873398F6B6FF37BAECDDA8812187CEAE13A9A0F722D637B253";
+ attribute INIT_0C of inst : label is "24005466854A113B09F36379249B3DA22B9B4C385D743EE536C7403C7B891E9B";
+ attribute INIT_0D of inst : label is "240059E7958A37B44F343F3A3D395F2550FB40F97FFB3EFB06FB790444B963FB";
+ attribute INIT_0E of inst : label is "98006ADC7A14CD09F2890774ECAA9486CB4AC4B5865DE475DAA9E570A3829879";
+ attribute INIT_0F of inst : label is "BFFF4000BFFFA000A000A000A3FFA3FFA3FFA3FFA3FFA3FFA3FFA3FFA3FFA3FF";
+ begin
+ inst : ramb4_s1
+ --pragma translate_off
+ generic map (
+ INIT_00 => romgen_str2slv(inst'INIT_00),
+ INIT_01 => romgen_str2slv(inst'INIT_01),
+ INIT_02 => romgen_str2slv(inst'INIT_02),
+ INIT_03 => romgen_str2slv(inst'INIT_03),
+ INIT_04 => romgen_str2slv(inst'INIT_04),
+ INIT_05 => romgen_str2slv(inst'INIT_05),
+ INIT_06 => romgen_str2slv(inst'INIT_06),
+ INIT_07 => romgen_str2slv(inst'INIT_07),
+ INIT_08 => romgen_str2slv(inst'INIT_08),
+ INIT_09 => romgen_str2slv(inst'INIT_09),
+ INIT_0A => romgen_str2slv(inst'INIT_0A),
+ INIT_0B => romgen_str2slv(inst'INIT_0B),
+ INIT_0C => romgen_str2slv(inst'INIT_0C),
+ INIT_0D => romgen_str2slv(inst'INIT_0D),
+ INIT_0E => romgen_str2slv(inst'INIT_0E),
+ INIT_0F => romgen_str2slv(inst'INIT_0F)
+ )
+ --pragma translate_on
+ port map (
+ DO => DATA(0 downto 0),
+ DI => "0",
+ ADDR => rom_addr,
+ WE => '0',
+ EN => '1',
+ RST => '0',
+ CLK => CLK
+ );
+ end generate;
+ rom1 : if true generate
+ attribute INIT_00 of inst : label is "6000872EB8D53E8A305A5340563544CF31412DCA42242A045945633A5945238A";
+ attribute INIT_01 of inst : label is "47FFBA234D6A417567A5AEBFCDCABB358EBEB275FDDA95FAA6B29DC5E6BADD45";
+ attribute INIT_02 of inst : label is "DFFFBCD9470DD4AACC4AFD25A1B4A647D245C9CA9634C224F845A7BA9945E58A";
+ attribute INIT_03 of inst : label is "BC00472EB0F6BB5593B542DA5E4B59B02DBE363569DA3DFA46B278C566BA1A45";
+ attribute INIT_04 of inst : label is "A00048D1AF1D448A6C5A394A222525FA51CA4DBE0345694F3DDA22741DDA6230";
+ attribute INIT_05 of inst : label is "5FFFA727786BA8E2B50ACD2441B56ECA134A11BA7645024F29DA463479DA6230";
+ attribute INIT_06 of inst : label is "67FFFF27C929788A7C51CD4AC24AE5B591B58E45C1BA89B0B625C1CAD625E9CA";
+ attribute INIT_07 of inst : label is "D3FF8F230F95E6556AAEF2A5FDB5E25AAE5A91B5CE4AB3DA89B2BE47C9BED645";
+ attribute INIT_08 of inst : label is "A8006F71EFE2176AEB5574757AD5584A224A7FB5745A4E7A31B40E4B31B54E47";
+ attribute INIT_09 of inst : label is "F4009EDCA914E972FB55C1354AB53C7962B5594217B57FA5410B6EB4304A0FB9";
+ attribute INIT_0A of inst : label is "840016A63AEDCC6AB76A588B6B550B7944B51B4A59A5238A1D5A62A75C5D07A6";
+ attribute INIT_0B of inst : label is "EFFFCB58AC12E5EA610DB52B60555D6630DD73AA3564428A7CD50BAA15552E8A";
+ attribute INIT_0C of inst : label is "00003C38572CC2EDCDE57E9295F28A14BE0D9A2DDA69E717D0EA99D6A61DB8F2";
+ attribute INIT_0D of inst : label is "97FF2C475353AF665F19DB139EEDBCE983EDF3EDB3ED8C128BEDF2E9F412CFED";
+ attribute INIT_0E of inst : label is "E800E060F4581E5190AE25D8128C05570E2C756648D135262E8D0BD90953112E";
+ attribute INIT_0F of inst : label is "80003FFF7FFF6000600060006000600060006000600060006000600060006000";
+ begin
+ inst : ramb4_s1
+ --pragma translate_off
+ generic map (
+ INIT_00 => romgen_str2slv(inst'INIT_00),
+ INIT_01 => romgen_str2slv(inst'INIT_01),
+ INIT_02 => romgen_str2slv(inst'INIT_02),
+ INIT_03 => romgen_str2slv(inst'INIT_03),
+ INIT_04 => romgen_str2slv(inst'INIT_04),
+ INIT_05 => romgen_str2slv(inst'INIT_05),
+ INIT_06 => romgen_str2slv(inst'INIT_06),
+ INIT_07 => romgen_str2slv(inst'INIT_07),
+ INIT_08 => romgen_str2slv(inst'INIT_08),
+ INIT_09 => romgen_str2slv(inst'INIT_09),
+ INIT_0A => romgen_str2slv(inst'INIT_0A),
+ INIT_0B => romgen_str2slv(inst'INIT_0B),
+ INIT_0C => romgen_str2slv(inst'INIT_0C),
+ INIT_0D => romgen_str2slv(inst'INIT_0D),
+ INIT_0E => romgen_str2slv(inst'INIT_0E),
+ INIT_0F => romgen_str2slv(inst'INIT_0F)
+ )
+ --pragma translate_on
+ port map (
+ DO => DATA(1 downto 1),
+ DI => "0",
+ ADDR => rom_addr,
+ WE => '0',
+ EN => '1',
+ RST => '0',
+ CLK => CLK
+ );
+ end generate;
+ rom2 : if true generate
+ attribute INIT_00 of inst : label is "1FFF714F62A6C55386D3982CA919D329A8D2D8D3A5099AD6C729E413F8D6DB6C";
+ attribute INIT_01 of inst : label is "3FFF7443D233FBD99689C96CBB2C97E69993D519A72CB0D39E648729E193F8D6";
+ attribute INIT_02 of inst : label is "3FFF7661DA51FA8CB52CCBF6F7668ED69529E72CCEE6A50998D69F6C8729E093";
+ attribute INIT_03 of inst : label is "7C00CEB09D58BE26F96676D356D22899476C2EE658D3672C219B18D61E6C0529";
+ attribute INIT_04 of inst : label is "6000C99E8DAE05536AD3302C0909732C68D31893252958D6672C651978D31AE6";
+ attribute INIT_05 of inst : label is "C0009147223352CC042C0BF7B766C6D3952CF76CAED6A52998D3DEE6E72CE519";
+ attribute INIT_06 of inst : label is "DFFFB6B85D8EFD53BAD9F42CC92CB366E8999929E76CD899EEF6A72CB10998D3";
+ attribute INIT_07 of inst : label is "B0004943A2599A26517706893499492C06D36899192C2AD32764192958934ED6";
+ attribute INIT_08 of inst : label is "5800A941424C8A33D1D9052631266ED3092C696616D3192C289926D217665929";
+ attribute INIT_09 of inst : label is "AC003860C5A75DDCDE26BB990E99352E3699502C6966168917D23966292C2691";
+ attribute INIT_0A of inst : label is "13FF083834B19E3355CCBD5391D98E2E8A99AE2CD176F6ACEBD38976952E9688";
+ attribute INIT_0B of inst : label is "C800AF60685C0E4C72515673DDD9C23782AEFE73C5C88F53B2A6B18CA5D98F53";
+ attribute INIT_0C of inst : label is "6400EF40E8B0784E76464FA36E5C645824517B8E043123A6334C3A581C5104A3";
+ attribute INIT_0D of inst : label is "2BFF4887A09CE4B8475E88A3284E284E544E2BB1144E185C1BB16BB16FA3644E";
+ attribute INIT_0E of inst : label is "5400AE806A9F5161E1CF409FC1CFBB67CEB0BB47B19E84B88E318F618F639F4F";
+ attribute INIT_0F of inst : label is "8000000000001FFF1FFF1FFF1FFF1FFF1FFF1FFF1FFF1FFF1FFF1FFF1FFF1FFF";
+ begin
+ inst : ramb4_s1
+ --pragma translate_off
+ generic map (
+ INIT_00 => romgen_str2slv(inst'INIT_00),
+ INIT_01 => romgen_str2slv(inst'INIT_01),
+ INIT_02 => romgen_str2slv(inst'INIT_02),
+ INIT_03 => romgen_str2slv(inst'INIT_03),
+ INIT_04 => romgen_str2slv(inst'INIT_04),
+ INIT_05 => romgen_str2slv(inst'INIT_05),
+ INIT_06 => romgen_str2slv(inst'INIT_06),
+ INIT_07 => romgen_str2slv(inst'INIT_07),
+ INIT_08 => romgen_str2slv(inst'INIT_08),
+ INIT_09 => romgen_str2slv(inst'INIT_09),
+ INIT_0A => romgen_str2slv(inst'INIT_0A),
+ INIT_0B => romgen_str2slv(inst'INIT_0B),
+ INIT_0C => romgen_str2slv(inst'INIT_0C),
+ INIT_0D => romgen_str2slv(inst'INIT_0D),
+ INIT_0E => romgen_str2slv(inst'INIT_0E),
+ INIT_0F => romgen_str2slv(inst'INIT_0F)
+ )
+ --pragma translate_on
+ port map (
+ DO => DATA(2 downto 2),
+ DI => "0",
+ ADDR => rom_addr,
+ WE => '0',
+ EN => '1',
+ RST => '0',
+ CLK => CLK
+ );
+ end generate;
+ rom3 : if true generate
+ attribute INIT_00 of inst : label is "F3FFB78FE5C7C09C026364B0CB5EE34EF463AB9C8CB19667D34EF35CEB98E8B0";
+ attribute INIT_01 of inst : label is "F3FFB683C543C49E023174B0CB4FA347D423A35E8CB09C639247934EF3DCEB98";
+ attribute INIT_02 of inst : label is "F3FFB681C561C5CF00B074B8C347B267DCB1B34FADB88CB19467934F934EF3DC";
+ attribute INIT_03 of inst : label is "F00086C08760854704B8FD9C626334214CB072472B9C0CB00C231467124F134E";
+ attribute INIT_04 of inst : label is "EC0080E097303F63959CBB4F34B13CB04B9C5423734E2B980CB00CA114631647";
+ attribute INIT_05 of inst : label is "CC00C8781ABC3A70FF4F8B473CB80D9C234F5CB07267734E6B9C2DB80CB00CA1";
+ attribute INIT_06 of inst : label is "CC00C93F38CF389CFA6180B00B4F434734212B4E4CB054217247734F634E6B9C";
+ attribute INIT_07 of inst : label is "83FF7F836561454744B87DCEC021F4B0CD9CB421AB4F899C8CB894B1D423D267";
+ attribute INIT_08 of inst : label is "3400207EDA8FBABC3B6180B83B470A6334B04B475D9C54B07421726363472B4E";
+ attribute INIT_09 of inst : label is "6FFFCE80A7380760C547FB21F5DEBF4FC2219B4FB4B8A231A3638B478B4F8DDE";
+ attribute INIT_0A of inst : label is "BC000EC0963E86BCCF70F89C7B610AB075DE4AB01B473DCF349C34B820B02230";
+ attribute INIT_0B of inst : label is "6BFF9180BE9F668F2A9E3143B89EC547FA308543808F8A9CBA38BB30BF61B563";
+ attribute INIT_0C of inst : label is "80005D800EC051706978E6C3269F5960669E3D3039411AC70A8F029F069E063C";
+ attribute INIT_0D of inst : label is "FBFF9AF8811FCAC056601EC35E8F2170768F5D3E4970416042C122C126C3268F";
+ attribute INIT_0E of inst : label is "080074FF58E0DD81BEF0CAE02EF011875F3F6E786EE06AC060C161816183718F";
+ attribute INIT_0F of inst : label is "800040003C00D7FFABFFA000BBFFBBFFBBFFBBFFBBFFBBFFBBFFBBFFBBFFBBFF";
+ begin
+ inst : ramb4_s1
+ --pragma translate_off
+ generic map (
+ INIT_00 => romgen_str2slv(inst'INIT_00),
+ INIT_01 => romgen_str2slv(inst'INIT_01),
+ INIT_02 => romgen_str2slv(inst'INIT_02),
+ INIT_03 => romgen_str2slv(inst'INIT_03),
+ INIT_04 => romgen_str2slv(inst'INIT_04),
+ INIT_05 => romgen_str2slv(inst'INIT_05),
+ INIT_06 => romgen_str2slv(inst'INIT_06),
+ INIT_07 => romgen_str2slv(inst'INIT_07),
+ INIT_08 => romgen_str2slv(inst'INIT_08),
+ INIT_09 => romgen_str2slv(inst'INIT_09),
+ INIT_0A => romgen_str2slv(inst'INIT_0A),
+ INIT_0B => romgen_str2slv(inst'INIT_0B),
+ INIT_0C => romgen_str2slv(inst'INIT_0C),
+ INIT_0D => romgen_str2slv(inst'INIT_0D),
+ INIT_0E => romgen_str2slv(inst'INIT_0E),
+ INIT_0F => romgen_str2slv(inst'INIT_0F)
+ )
+ --pragma translate_on
+ port map (
+ DO => DATA(3 downto 3),
+ DI => "0",
+ ADDR => rom_addr,
+ WE => '0',
+ EN => '1',
+ RST => '0',
+ CLK => CLK
+ );
+ end generate;
+ rom4 : if true generate
+ attribute INIT_00 of inst : label is "9400220F52F8B2E00F7C8D3F799F0E703283391F3D3E2F786E704E6046E046C0";
+ attribute INIT_01 of inst : label is "94002303727CB2E00F3E8D3F798F4E7812C3319F3D3F2D7C2F782E704EE046E0";
+ attribute INIT_02 of inst : label is "94002301727EB2F00D3F8D3F71874F7812C1318F3D3F3D3E2D782E702E704EE0";
+ attribute INIT_03 of inst : label is "97FF1300327FF2780D3F8D1FF083CD3E82C0B087B91FBD3FBD3CAD78AF70AE70";
+ attribute INIT_04 of inst : label is "87FF1500323F727C0D1FC98FB2C1CD3F86E092C3B18FB91FBD3FBD3EAD7CAF78";
+ attribute INIT_05 of inst : label is "A7FF1580B73F777F0D8FF987B2C0FD1FCE7092C0B087B18FB91FBD3FBD3FBD3E";
+ attribute INIT_06 of inst : label is "A7FF15C0B50F751F0881F2C08670F187CD3EC67082C092C1B087B18FB18FB91F";
+ attribute INIT_07 of inst : label is "EBFF95FCAD814D87B2C072F08D3EF2C0FD1FCD3EC670C6E0C2C0D2C192C39087";
+ attribute INIT_08 of inst : label is "6800CA7F88F008C0F67E0D3F4987077C32C079876D1F6D3F4D3E4F7C4E784670";
+ attribute INIT_09 of inst : label is "7800EB00D23FB27FCD8709C172E04D8F0F3E167032C030C131833987398F3D1F";
+ attribute INIT_0A of inst : label is "17FF14FF3CC0CCC0327FF51F8981873FF2E0F8C0E987CD0FCD1FCD3FCD3FCF3F";
+ attribute INIT_0B of inst : label is "43FF9A002B1F530FE8E0027CF51FB27888C08D838D0F871FB73FB63FB27EB27C";
+ attribute INIT_0C of inst : label is "37FF2600EB0085802A7FD303ECE0B580931F8A3F8A7E88F888F088E08CE08CC0";
+ attribute INIT_0D of inst : label is "33FF5CFF9A1FEB00FC7F4B0334F01580430F4A3F4A7F4A7F48FE68FE6CFC6CF0";
+ attribute INIT_0E of inst : label is "F000B700DCFFC60124FF6B0054FF45F80BC02B802B002B002B012A012A033A0F";
+ attribute INIT_0F of inst : label is "DFFFC000300097FF83FF87FF9C009C009C009C009C009C009C009C009C009C00";
+ begin
+ inst : ramb4_s1
+ --pragma translate_off
+ generic map (
+ INIT_00 => romgen_str2slv(inst'INIT_00),
+ INIT_01 => romgen_str2slv(inst'INIT_01),
+ INIT_02 => romgen_str2slv(inst'INIT_02),
+ INIT_03 => romgen_str2slv(inst'INIT_03),
+ INIT_04 => romgen_str2slv(inst'INIT_04),
+ INIT_05 => romgen_str2slv(inst'INIT_05),
+ INIT_06 => romgen_str2slv(inst'INIT_06),
+ INIT_07 => romgen_str2slv(inst'INIT_07),
+ INIT_08 => romgen_str2slv(inst'INIT_08),
+ INIT_09 => romgen_str2slv(inst'INIT_09),
+ INIT_0A => romgen_str2slv(inst'INIT_0A),
+ INIT_0B => romgen_str2slv(inst'INIT_0B),
+ INIT_0C => romgen_str2slv(inst'INIT_0C),
+ INIT_0D => romgen_str2slv(inst'INIT_0D),
+ INIT_0E => romgen_str2slv(inst'INIT_0E),
+ INIT_0F => romgen_str2slv(inst'INIT_0F)
+ )
+ --pragma translate_on
+ port map (
+ DO => DATA(4 downto 4),
+ DI => "0",
+ ADDR => rom_addr,
+ WE => '0',
+ EN => '1',
+ RST => '0',
+ CLK => CLK
+ );
+ end generate;
+ rom5 : if true generate
+ attribute INIT_00 of inst : label is "B800140FB4FFF4FF847F79C0021F047F34FC3DE039C03B807B807B807B007B00";
+ attribute INIT_01 of inst : label is "B8001403B47FF4FF843F79C0020F047F14FC35E039C039803B803B807B007B00";
+ attribute INIT_02 of inst : label is "B8001401B47FF4FF863F79C00A07047F14FE35F039C039C039803B803B807B00";
+ attribute INIT_03 of inst : label is "B8003400F47FF47F863F79E00B03063F04FF34F83DE039C039C039803B803B80";
+ attribute INIT_04 of inst : label is "A8003600F43F747F861F7DF04B01063F04FF14FC35F03DE039C039C039803B80";
+ attribute INIT_05 of inst : label is "A8003600F43F747F860F7DF84B00061F047F14FF34F835F03DE039C039C039C0";
+ attribute INIT_06 of inst : label is "A8003600F60F761F830174FF7B800A07063F047F04FF14FE34F835F035F03DE0";
+ attribute INIT_07 of inst : label is "AC003600E60146078B00F4FF79C00B00061F063F047F04FF04FF14FE14FC14F8";
+ attribute INIT_08 of inst : label is "2FFF2380C30003008B80863FFDF8FB80CB008207861F863F863F847F847F847F";
+ attribute INIT_09 of inst : label is "2FFF23FFCBC00B80B9F88201F4FFF9F0FBC0EB80CB00CB01CA03C207C20FC61F";
+ attribute INIT_0A of inst : label is "47FFC8FF08FF38FF747F89E08201843FF4FFFCFFFDF8F9F0F9E0F9C0F9C0FBC0";
+ attribute INIT_0B of inst : label is "13FF4C001C1FB40F6300747F89E08B8083008603860F841FB43FB43FB47FB47F";
+ attribute INIT_0C of inst : label is "5800D7FF23FFC9FF9C7F4BFC67007600741F7C3F7C7F7CFF7CFF7CFF78FF78FF";
+ attribute INIT_0D of inst : label is "A3FF0F00B3E023FF487F43FC77007600340F3C3F3C7F3C7F3CFF1CFF18FF18FF";
+ attribute INIT_0E of inst : label is "9FFF58000F00F7FEE8FFA3FFB700B600BC009C009C009C009C019C019C038C0F";
+ attribute INIT_0F of inst : label is "DFFFA0005FFF87FFAC00A800B000B000B000B000B000B000B000B000B000B000";
+ begin
+ inst : ramb4_s1
+ --pragma translate_off
+ generic map (
+ INIT_00 => romgen_str2slv(inst'INIT_00),
+ INIT_01 => romgen_str2slv(inst'INIT_01),
+ INIT_02 => romgen_str2slv(inst'INIT_02),
+ INIT_03 => romgen_str2slv(inst'INIT_03),
+ INIT_04 => romgen_str2slv(inst'INIT_04),
+ INIT_05 => romgen_str2slv(inst'INIT_05),
+ INIT_06 => romgen_str2slv(inst'INIT_06),
+ INIT_07 => romgen_str2slv(inst'INIT_07),
+ INIT_08 => romgen_str2slv(inst'INIT_08),
+ INIT_09 => romgen_str2slv(inst'INIT_09),
+ INIT_0A => romgen_str2slv(inst'INIT_0A),
+ INIT_0B => romgen_str2slv(inst'INIT_0B),
+ INIT_0C => romgen_str2slv(inst'INIT_0C),
+ INIT_0D => romgen_str2slv(inst'INIT_0D),
+ INIT_0E => romgen_str2slv(inst'INIT_0E),
+ INIT_0F => romgen_str2slv(inst'INIT_0F)
+ )
+ --pragma translate_on
+ port map (
+ DO => DATA(5 downto 5),
+ DI => "0",
+ ADDR => rom_addr,
+ WE => '0',
+ EN => '1',
+ RST => '0',
+ CLK => CLK
+ );
+ end generate;
+ rom6 : if true generate
+ attribute INIT_00 of inst : label is "9FFF180F18FFE700E87F91FF93E09780A700AE00AE00AC00EC00EC00EC00EC00";
+ attribute INIT_01 of inst : label is "9FFF1803187FE700E83F91FF93F097808700A600AE00AE00AC00AC00EC00EC00";
+ attribute INIT_02 of inst : label is "9FFF1801187FE700E83F91FF93F897808700A600AE00AE00AE00AC00AC00EC00";
+ attribute INIT_03 of inst : label is "9FFF1800187FE780E83F91FF93FC97C09700A700AE00AE00AE00AE00AC00AC00";
+ attribute INIT_04 of inst : label is "8FFF1800183F6780E81F91FF93FE97C097008700A600AE00AE00AE00AE00AC00";
+ attribute INIT_05 of inst : label is "8FFF1800183F6780E80F91FF93FF97E097808700A700A600AE00AE00AE00AE00";
+ attribute INIT_06 of inst : label is "8FFF1800180F67E0EC0198FF93FF93F897C0978097008700A700A600A600AE00";
+ attribute INIT_07 of inst : label is "8FFF1800080157F8EC0098FF91FF93FF97E097C0978097009700870087008700";
+ attribute INIT_08 of inst : label is "0FFF0C002C0013FFEC00E83F91FF93FF93FF93F897E097C097C0978097809780";
+ attribute INIT_09 of inst : label is "0FFF0C002C0013FFEE00EC0198FF91FF93FF93FF93FF93FE93FC93F893F097E0";
+ attribute INIT_0A of inst : label is "27FF2F00EF0010FF6780EE00EC01E83F98FF90FF91FF91FF91FF91FF91FF93FF";
+ attribute INIT_0B of inst : label is "23FF2FFFEFE0180F73FF6780EE00EC00EC00E803E80FE81FD83FD83FD87FD87F";
+ attribute INIT_0C of inst : label is "200027FFF3FF2E00107F53FF77FF67FF67E06FC06F806F006F006F006F006F00";
+ attribute INIT_0D of inst : label is "7C00D0009C00F3FFAF80AC0098009800980F903F907F907F90FF90FF90FF90FF";
+ attribute INIT_0E of inst : label is "A0002000D00027FF0F000C00180018001000100010001000100110011003100F";
+ attribute INIT_0F of inst : label is "9FFF40002000A7FF8FFF8FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF";
+ begin
+ inst : ramb4_s1
+ --pragma translate_off
+ generic map (
+ INIT_00 => romgen_str2slv(inst'INIT_00),
+ INIT_01 => romgen_str2slv(inst'INIT_01),
+ INIT_02 => romgen_str2slv(inst'INIT_02),
+ INIT_03 => romgen_str2slv(inst'INIT_03),
+ INIT_04 => romgen_str2slv(inst'INIT_04),
+ INIT_05 => romgen_str2slv(inst'INIT_05),
+ INIT_06 => romgen_str2slv(inst'INIT_06),
+ INIT_07 => romgen_str2slv(inst'INIT_07),
+ INIT_08 => romgen_str2slv(inst'INIT_08),
+ INIT_09 => romgen_str2slv(inst'INIT_09),
+ INIT_0A => romgen_str2slv(inst'INIT_0A),
+ INIT_0B => romgen_str2slv(inst'INIT_0B),
+ INIT_0C => romgen_str2slv(inst'INIT_0C),
+ INIT_0D => romgen_str2slv(inst'INIT_0D),
+ INIT_0E => romgen_str2slv(inst'INIT_0E),
+ INIT_0F => romgen_str2slv(inst'INIT_0F)
+ )
+ --pragma translate_on
+ port map (
+ DO => DATA(6 downto 6),
+ DI => "0",
+ ADDR => rom_addr,
+ WE => '0',
+ EN => '1',
+ RST => '0',
+ CLK => CLK
+ );
+ end generate;
+ rom7 : if true generate
+ attribute INIT_00 of inst : label is "20005FF0A0FF47FF4F805E005C00580078007000700070003000300030003000";
+ attribute INIT_01 of inst : label is "20005FFCA07F47FF4FC05E005C00580058007800700070007000700030003000";
+ attribute INIT_02 of inst : label is "20005FFEA07F47FF4FC05E005C00580058007800700070007000700070003000";
+ attribute INIT_03 of inst : label is "20005FFFA07F47FF4FC05E005C00580058007800700070007000700070007000";
+ attribute INIT_04 of inst : label is "30005FFFA03FC7FF4FE05E005C00580058005800780070007000700070007000";
+ attribute INIT_05 of inst : label is "30005FFFA03FC7FF4FF05E005C00580058005800780078007000700070007000";
+ attribute INIT_06 of inst : label is "30005FFFA00FC7FF4FFE5F005C005C0058005800580058007800780078007000";
+ attribute INIT_07 of inst : label is "30005FFFB001E7FF4FFF5F005E005C0058005800580058005800580058005800";
+ attribute INIT_08 of inst : label is "B0004FFFB000A3FF4FFF4FC05E005C005C005C00580058005800580058005800";
+ attribute INIT_09 of inst : label is "B0004FFFB000A3FF4FFF4FFE5F005E005C005C005C005C005C005C005C005800";
+ attribute INIT_0A of inst : label is "B8004FFFB000A0FFC7FF4FFF4FFE4FC05F005F005E005E005E005E005E005C00";
+ attribute INIT_0B of inst : label is "BC004FFFB000A00FC3FFC7FF4FFF4FFF4FFF4FFC4FF04FE05FC05FC05F805F80";
+ attribute INIT_0C of inst : label is "BFFF47FFBC00B000A07FE3FFC7FFC7FFC7FFCFFFCFFFCFFFCFFFCFFFCFFFCFFF";
+ attribute INIT_0D of inst : label is "BFFF6000DFFFBC00B000B000A000A000A00FA03FA07FA07FA0FFA0FFA0FFA0FF";
+ attribute INIT_0E of inst : label is "C000BFFF600047FF4FFF4FFF5FFF5FFF5FFF5FFF5FFF5FFF5FFE5FFE5FFC5FF0";
+ attribute INIT_0F of inst : label is "E0008000BFFF3800300030002000200020002000200020002000200020002000";
+ begin
+ inst : ramb4_s1
+ --pragma translate_off
+ generic map (
+ INIT_00 => romgen_str2slv(inst'INIT_00),
+ INIT_01 => romgen_str2slv(inst'INIT_01),
+ INIT_02 => romgen_str2slv(inst'INIT_02),
+ INIT_03 => romgen_str2slv(inst'INIT_03),
+ INIT_04 => romgen_str2slv(inst'INIT_04),
+ INIT_05 => romgen_str2slv(inst'INIT_05),
+ INIT_06 => romgen_str2slv(inst'INIT_06),
+ INIT_07 => romgen_str2slv(inst'INIT_07),
+ INIT_08 => romgen_str2slv(inst'INIT_08),
+ INIT_09 => romgen_str2slv(inst'INIT_09),
+ INIT_0A => romgen_str2slv(inst'INIT_0A),
+ INIT_0B => romgen_str2slv(inst'INIT_0B),
+ INIT_0C => romgen_str2slv(inst'INIT_0C),
+ INIT_0D => romgen_str2slv(inst'INIT_0D),
+ INIT_0E => romgen_str2slv(inst'INIT_0E),
+ INIT_0F => romgen_str2slv(inst'INIT_0F)
+ )
+ --pragma translate_on
+ port map (
+ DO => DATA(7 downto 7),
+ DI => "0",
+ ADDR => rom_addr,
+ WE => '0',
+ EN => '1',
+ RST => '0',
+ CLK => CLK
+ );
+ end generate;
+ rom8 : if true generate
+ attribute INIT_00 of inst : label is "C0009FFF3F007800700060006000600040004000400040004000400040004000";
+ attribute INIT_01 of inst : label is "C0009FFF3F807800700060006000600060004000400040004000400040004000";
+ attribute INIT_02 of inst : label is "C0009FFF3F807800700060006000600060004000400040004000400040004000";
+ attribute INIT_03 of inst : label is "C0009FFF3F807800700060006000600060004000400040004000400040004000";
+ attribute INIT_04 of inst : label is "C0009FFF3FC07800700060006000600060006000400040004000400040004000";
+ attribute INIT_05 of inst : label is "C0009FFF3FC07800700060006000600060006000400040004000400040004000";
+ attribute INIT_06 of inst : label is "C0009FFF3FF07800700060006000600060006000600060004000400040004000";
+ attribute INIT_07 of inst : label is "C0009FFF3FFE7800700060006000600060006000600060006000600060006000";
+ attribute INIT_08 of inst : label is "C0008FFF3FFF3C00700070006000600060006000600060006000600060006000";
+ attribute INIT_09 of inst : label is "C0008FFF3FFF3C00700070006000600060006000600060006000600060006000";
+ attribute INIT_0A of inst : label is "C0008FFF3FFF3F00780070007000700060006000600060006000600060006000";
+ attribute INIT_0B of inst : label is "C0008FFF3FFF3FF07C0078007000700070007000700070006000600060006000";
+ attribute INIT_0C of inst : label is "C00087FF3FFF3FFF3F807C007800780078007000700070007000700070007000";
+ attribute INIT_0D of inst : label is "C00080001FFF3FFF3FFF3FFF3FFF3FFF3FF03FC03F803F803F003F003F003F00";
+ attribute INIT_0E of inst : label is "FFFFC000800087FF8FFF8FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF9FFF";
+ attribute INIT_0F of inst : label is "FFFFFFFFC000C000C000C000C000C000C000C000C000C000C000C000C000C000";
+ begin
+ inst : ramb4_s1
+ --pragma translate_off
+ generic map (
+ INIT_00 => romgen_str2slv(inst'INIT_00),
+ INIT_01 => romgen_str2slv(inst'INIT_01),
+ INIT_02 => romgen_str2slv(inst'INIT_02),
+ INIT_03 => romgen_str2slv(inst'INIT_03),
+ INIT_04 => romgen_str2slv(inst'INIT_04),
+ INIT_05 => romgen_str2slv(inst'INIT_05),
+ INIT_06 => romgen_str2slv(inst'INIT_06),
+ INIT_07 => romgen_str2slv(inst'INIT_07),
+ INIT_08 => romgen_str2slv(inst'INIT_08),
+ INIT_09 => romgen_str2slv(inst'INIT_09),
+ INIT_0A => romgen_str2slv(inst'INIT_0A),
+ INIT_0B => romgen_str2slv(inst'INIT_0B),
+ INIT_0C => romgen_str2slv(inst'INIT_0C),
+ INIT_0D => romgen_str2slv(inst'INIT_0D),
+ INIT_0E => romgen_str2slv(inst'INIT_0E),
+ INIT_0F => romgen_str2slv(inst'INIT_0F)
+ )
+ --pragma translate_on
+ port map (
+ DO => DATA(8 downto 8),
+ DI => "0",
+ ADDR => rom_addr,
+ WE => '0',
+ EN => '1',
+ RST => '0',
+ CLK => CLK
+ );
+ end generate;
+ rom9 : if true generate
+ attribute INIT_00 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
+ attribute INIT_01 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
+ attribute INIT_02 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
+ attribute INIT_03 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
+ attribute INIT_04 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
+ attribute INIT_05 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
+ attribute INIT_06 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
+ attribute INIT_07 of inst : label is "FFFFE000C0008000800080008000800080008000800080008000800080008000";
+ attribute INIT_08 of inst : label is "FFFFF000C000C000800080008000800080008000800080008000800080008000";
+ attribute INIT_09 of inst : label is "FFFFF000C000C000800080008000800080008000800080008000800080008000";
+ attribute INIT_0A of inst : label is "FFFFF000C000C000800080008000800080008000800080008000800080008000";
+ attribute INIT_0B of inst : label is "FFFFF000C000C000800080008000800080008000800080008000800080008000";
+ attribute INIT_0C of inst : label is "FFFFF800C000C000C00080008000800080008000800080008000800080008000";
+ attribute INIT_0D of inst : label is "FFFFFFFFE000C000C000C000C000C000C000C000C000C000C000C000C000C000";
+ attribute INIT_0E of inst : label is "FFFFFFFFFFFFF800F000F000E000E000E000E000E000E000E000E000E000E000";
+ attribute INIT_0F of inst : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
+ begin
+ inst : ramb4_s1
+ --pragma translate_off
+ generic map (
+ INIT_00 => romgen_str2slv(inst'INIT_00),
+ INIT_01 => romgen_str2slv(inst'INIT_01),
+ INIT_02 => romgen_str2slv(inst'INIT_02),
+ INIT_03 => romgen_str2slv(inst'INIT_03),
+ INIT_04 => romgen_str2slv(inst'INIT_04),
+ INIT_05 => romgen_str2slv(inst'INIT_05),
+ INIT_06 => romgen_str2slv(inst'INIT_06),
+ INIT_07 => romgen_str2slv(inst'INIT_07),
+ INIT_08 => romgen_str2slv(inst'INIT_08),
+ INIT_09 => romgen_str2slv(inst'INIT_09),
+ INIT_0A => romgen_str2slv(inst'INIT_0A),
+ INIT_0B => romgen_str2slv(inst'INIT_0B),
+ INIT_0C => romgen_str2slv(inst'INIT_0C),
+ INIT_0D => romgen_str2slv(inst'INIT_0D),
+ INIT_0E => romgen_str2slv(inst'INIT_0E),
+ INIT_0F => romgen_str2slv(inst'INIT_0F)
+ )
+ --pragma translate_on
+ port map (
+ DO => DATA(9 downto 9),
+ DI => "0",
+ ADDR => rom_addr,
+ WE => '0',
+ EN => '1',
+ RST => '0',
+ CLK => CLK
+ );
+ end generate;
+end RTL;
diff --git a/ym2149/vol_table_001.txt b/ym2149/vol_table_001.txt
new file mode 100644
index 0000000..ce9638e
--- /dev/null
+++ b/ym2149/vol_table_001.txt
@@ -0,0 +1,301 @@
+3FF 3B0 381 371 371 371 371 371 371 371 371 371 371 371 371 371
+3B0 359 322 302 302 302 302 302 302 302 302 302 302 302 302 302
+381 322 2DB 2BB 2AB 2AB 2A3 2A3 2A3 2A3 2A3 2A3 2A3 2A3 2A3 2A3
+379 30A 2C3 29C 284 27C 27C 27C 27C 27C 27C 27C 27C 27C 27C 27C
+379 302 2AB 284 26C 264 25C 25C 25C 25C 25C 25C 25C 25C 25C 25C
+379 302 2AB 284 264 254 254 254 254 254 254 254 254 254 254 254
+379 302 2AB 27C 25C 254 24D 24D 24D 24D 24D 24D 24D 24D 24D 24D
+379 302 2AB 27C 25C 254 24D 24D 24D 24D 24D 24D 24D 24D 24D 24D
+379 302 2AB 27C 25C 254 24D 24D 24D 24D 24D 24D 24D 24D 24D 24D
+379 302 2AB 27C 25C 254 24D 24D 24D 24D 24D 24D 24D 24D 24D 24D
+379 302 2AB 27C 25C 254 24D 24D 24D 24D 24D 24D 24D 24D 24D 24D
+379 302 2AB 27C 25C 254 24D 24D 24D 24D 24D 24D 24D 24D 24D 24D
+379 302 2AB 27C 25C 254 24D 24D 24D 24D 24D 24D 24D 24D 24D 24D
+379 302 2AB 27C 25C 254 24D 24D 24D 24D 24D 24D 24D 24D 24D 24D
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+24D 19A 114 0D2 09D 082 06A 05C 050 049 042 03F 03C 03A 038 036
+24D 18E 108 0C5 091 073 05C 04D 042 03A 035 031 02E 02B 02A 027
+24D 188 0FE 0BB 085 068 050 042 035 02F 028 024 021 020 01D 01B
+24D 184 0FA 0B5 07E 062 049 03A 02F 027 021 01D 01A 018 016 014
+24D 182 0F5 0B0 079 05C 042 035 028 021 01B 018 014 012 010 00D
+24D 180 0F3 0AD 076 058 03F 031 024 01D 018 014 011 00E 00D 009
+24D 17F 0F0 0AB 073 055 03C 02E 021 01A 014 011 00D 00B 009 006
+24D 17E 0EF 0A9 071 054 03A 02B 020 018 012 00E 00B 009 007 004
+24D 17E 0ED 0A7 06F 051 038 02A 01D 016 010 00D 009 007 005 002
+24D 17D 0EB 0A5 06D 050 036 027 01B 014 00D 009 006 004 002 000
diff --git a/ym2149/vol_table_array.vhd b/ym2149/vol_table_array.vhd
new file mode 100644
index 0000000..ea644ea
--- /dev/null
+++ b/ym2149/vol_table_array.vhd
@@ -0,0 +1,540 @@
+-- generated with tablegen by MikeJ
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vol_table is
+ port (
+ CLK : in std_logic;
+ ADDR : in std_logic_vector(11 downto 0);
+ DATA : out std_logic_vector(9 downto 0)
+ );
+end;
+
+architecture RTL of vol_table is
+
+
+ type ROM_ARRAY is array(0 to 4095) of std_logic_vector(11 downto 0);
+ constant ROM : ROM_ARRAY := (
+ x"000",x"002",x"004",x"006",x"009",x"00D",x"014",x"01B", -- 0x0000
+ x"027",x"036",x"050",x"06D",x"0A5",x"0EB",x"17D",x"24D", -- 0x0008
+ x"002",x"005",x"007",x"009",x"00D",x"010",x"016",x"01D", -- 0x0010
+ x"02A",x"038",x"051",x"06F",x"0A7",x"0ED",x"17E",x"24D", -- 0x0018
+ x"004",x"007",x"009",x"00B",x"00E",x"012",x"018",x"020", -- 0x0020
+ x"02B",x"03A",x"054",x"071",x"0A9",x"0EF",x"17E",x"24D", -- 0x0028
+ x"006",x"009",x"00B",x"00D",x"011",x"014",x"01A",x"021", -- 0x0030
+ x"02E",x"03C",x"055",x"073",x"0AB",x"0F0",x"17F",x"24D", -- 0x0038
+ x"009",x"00D",x"00E",x"011",x"014",x"018",x"01D",x"024", -- 0x0040
+ x"031",x"03F",x"058",x"076",x"0AD",x"0F3",x"180",x"24D", -- 0x0048
+ x"00D",x"010",x"012",x"014",x"018",x"01B",x"021",x"028", -- 0x0050
+ x"035",x"042",x"05C",x"079",x"0B0",x"0F5",x"182",x"24D", -- 0x0058
+ x"014",x"016",x"018",x"01A",x"01D",x"021",x"027",x"02F", -- 0x0060
+ x"03A",x"049",x"062",x"07E",x"0B5",x"0FA",x"184",x"24D", -- 0x0068
+ x"01B",x"01D",x"020",x"021",x"024",x"028",x"02F",x"035", -- 0x0070
+ x"042",x"050",x"068",x"085",x"0BB",x"0FE",x"188",x"24D", -- 0x0078
+ x"027",x"02A",x"02B",x"02E",x"031",x"035",x"03A",x"042", -- 0x0080
+ x"04D",x"05C",x"073",x"091",x"0C5",x"108",x"18E",x"24D", -- 0x0088
+ x"036",x"038",x"03A",x"03C",x"03F",x"042",x"049",x"050", -- 0x0090
+ x"05C",x"06A",x"082",x"09D",x"0D2",x"114",x"19A",x"24D", -- 0x0098
+ x"050",x"051",x"054",x"055",x"058",x"05C",x"062",x"068", -- 0x00A0
+ x"073",x"082",x"098",x"0B4",x"0E7",x"128",x"1AB",x"254", -- 0x00A8
+ x"06D",x"06F",x"071",x"073",x"076",x"079",x"07E",x"085", -- 0x00B0
+ x"091",x"09D",x"0B4",x"0D0",x"102",x"142",x"1C1",x"264", -- 0x00B8
+ x"0A5",x"0A7",x"0A9",x"0AB",x"0AD",x"0B0",x"0B5",x"0BB", -- 0x00C0
+ x"0C5",x"0D2",x"0E7",x"102",x"133",x"172",x"1ED",x"27C", -- 0x00C8
+ x"0EB",x"0ED",x"0EF",x"0F0",x"0F3",x"0F5",x"0FA",x"0FE", -- 0x00D0
+ x"108",x"114",x"128",x"142",x"172",x"1AF",x"21D",x"2AB", -- 0x00D8
+ x"17D",x"17E",x"17E",x"17F",x"180",x"182",x"184",x"188", -- 0x00E0
+ x"18E",x"19A",x"1AB",x"1C1",x"1ED",x"21D",x"284",x"30A", -- 0x00E8
+ x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x00F0
+ x"24D",x"24D",x"254",x"264",x"27C",x"2AB",x"30A",x"379", -- 0x00F8
+ x"002",x"005",x"006",x"009",x"00C",x"010",x"016",x"01D", -- 0x0100
+ x"02A",x"038",x"052",x"06F",x"0A7",x"0ED",x"17E",x"24E", -- 0x0108
+ x"005",x"007",x"009",x"00B",x"00F",x"012",x"018",x"01F", -- 0x0110
+ x"02C",x"03A",x"053",x"071",x"0A9",x"0EF",x"17F",x"24E", -- 0x0118
+ x"006",x"009",x"00B",x"00D",x"011",x"014",x"01B",x"022", -- 0x0120
+ x"02E",x"03D",x"056",x"073",x"0AB",x"0F0",x"180",x"24E", -- 0x0128
+ x"009",x"00B",x"00D",x"010",x"013",x"016",x"01C",x"023", -- 0x0130
+ x"030",x"03E",x"057",x"075",x"0AD",x"0F2",x"181",x"24E", -- 0x0138
+ x"00C",x"00F",x"011",x"013",x"016",x"01A",x"01F",x"027", -- 0x0140
+ x"033",x"041",x"05B",x"078",x"0AF",x"0F4",x"181",x"24E", -- 0x0148
+ x"010",x"012",x"014",x"016",x"01A",x"01D",x"023",x"02A", -- 0x0150
+ x"037",x"044",x"05E",x"07B",x"0B2",x"0F7",x"183",x"24E", -- 0x0158
+ x"016",x"018",x"01B",x"01C",x"01F",x"023",x"02A",x"031", -- 0x0160
+ x"03D",x"04B",x"064",x"080",x"0B7",x"0FB",x"185",x"24E", -- 0x0168
+ x"01D",x"01F",x"022",x"023",x"027",x"02A",x"031",x"037", -- 0x0170
+ x"044",x"052",x"06A",x"087",x"0BD",x"100",x"189",x"24E", -- 0x0178
+ x"02A",x"02C",x"02E",x"030",x"033",x"037",x"03D",x"044", -- 0x0180
+ x"04F",x"05E",x"075",x"092",x"0C7",x"10A",x"190",x"24E", -- 0x0188
+ x"038",x"03A",x"03D",x"03E",x"041",x"044",x"04B",x"052", -- 0x0190
+ x"05E",x"06C",x"083",x"09F",x"0D4",x"115",x"19B",x"24E", -- 0x0198
+ x"052",x"053",x"056",x"057",x"05B",x"05E",x"064",x"06A", -- 0x01A0
+ x"075",x"083",x"09A",x"0B6",x"0E9",x"12A",x"1AD",x"256", -- 0x01A8
+ x"06F",x"071",x"073",x"075",x"078",x"07B",x"080",x"087", -- 0x01B0
+ x"092",x"09F",x"0B6",x"0D1",x"104",x"143",x"1C2",x"265", -- 0x01B8
+ x"0A7",x"0A9",x"0AB",x"0AD",x"0AF",x"0B2",x"0B7",x"0BD", -- 0x01C0
+ x"0C7",x"0D4",x"0E9",x"104",x"135",x"174",x"1EE",x"27D", -- 0x01C8
+ x"0ED",x"0EF",x"0F0",x"0F2",x"0F4",x"0F7",x"0FB",x"100", -- 0x01D0
+ x"10A",x"115",x"12A",x"143",x"174",x"1B0",x"21E",x"2AC", -- 0x01D8
+ x"17E",x"17F",x"180",x"181",x"181",x"183",x"185",x"189", -- 0x01E0
+ x"190",x"19B",x"1AD",x"1C2",x"1EE",x"21E",x"285",x"30B", -- 0x01E8
+ x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E", -- 0x01F0
+ x"24E",x"24E",x"256",x"265",x"27D",x"2AC",x"30B",x"379", -- 0x01F8
+ x"004",x"006",x"008",x"00A",x"00D",x"011",x"018",x"01F", -- 0x0200
+ x"02B",x"039",x"053",x"070",x"0A8",x"0EE",x"17F",x"24F", -- 0x0208
+ x"006",x"009",x"00B",x"00D",x"011",x"014",x"01A",x"021", -- 0x0210
+ x"02E",x"03C",x"055",x"073",x"0AB",x"0F0",x"180",x"24F", -- 0x0218
+ x"008",x"00B",x"00D",x"00F",x"012",x"016",x"01C",x"023", -- 0x0220
+ x"02F",x"03E",x"057",x"074",x"0AC",x"0F2",x"181",x"24F", -- 0x0228
+ x"00A",x"00D",x"00F",x"011",x"014",x"018",x"01E",x"025", -- 0x0230
+ x"031",x"040",x"059",x"077",x"0AE",x"0F3",x"182",x"24F", -- 0x0238
+ x"00D",x"011",x"012",x"014",x"018",x"01B",x"021",x"028", -- 0x0240
+ x"035",x"043",x"05C",x"079",x"0B0",x"0F5",x"183",x"24F", -- 0x0248
+ x"011",x"014",x"016",x"018",x"01B",x"01F",x"025",x"02C", -- 0x0250
+ x"039",x"046",x"05F",x"07C",x"0B3",x"0F8",x"184",x"24F", -- 0x0258
+ x"018",x"01A",x"01C",x"01E",x"021",x"025",x"02B",x"032", -- 0x0260
+ x"03E",x"04C",x"065",x"082",x"0B8",x"0FD",x"186",x"24F", -- 0x0268
+ x"01F",x"021",x"023",x"025",x"028",x"02C",x"032",x"039", -- 0x0270
+ x"045",x"053",x"06C",x"088",x"0BE",x"101",x"18A",x"24F", -- 0x0278
+ x"02B",x"02E",x"02F",x"031",x"035",x"039",x"03E",x"045", -- 0x0280
+ x"051",x"05F",x"077",x"094",x"0C8",x"10B",x"191",x"24F", -- 0x0288
+ x"039",x"03C",x"03E",x"040",x"043",x"046",x"04C",x"053", -- 0x0290
+ x"05F",x"06D",x"085",x"0A0",x"0D5",x"116",x"19C",x"24F", -- 0x0298
+ x"053",x"055",x"057",x"059",x"05C",x"05F",x"065",x"06C", -- 0x02A0
+ x"077",x"085",x"09B",x"0B7",x"0EA",x"12B",x"1AE",x"256", -- 0x02A8
+ x"070",x"073",x"074",x"077",x"079",x"07C",x"082",x"088", -- 0x02B0
+ x"094",x"0A0",x"0B7",x"0D3",x"105",x"144",x"1C3",x"266", -- 0x02B8
+ x"0A8",x"0AB",x"0AC",x"0AE",x"0B0",x"0B3",x"0B8",x"0BE", -- 0x02C0
+ x"0C8",x"0D5",x"0EA",x"105",x"136",x"175",x"1EF",x"27E", -- 0x02C8
+ x"0EE",x"0F0",x"0F2",x"0F3",x"0F5",x"0F8",x"0FC",x"101", -- 0x02D0
+ x"10B",x"116",x"12B",x"144",x"175",x"1B1",x"21F",x"2AD", -- 0x02D8
+ x"17F",x"180",x"181",x"182",x"183",x"184",x"186",x"18A", -- 0x02E0
+ x"191",x"19C",x"1AE",x"1C3",x"1EF",x"21F",x"285",x"30B", -- 0x02E8
+ x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E", -- 0x02F0
+ x"24E",x"24E",x"256",x"266",x"27E",x"2AD",x"30B",x"37A", -- 0x02F8
+ x"006",x"009",x"00A",x"00D",x"010",x"014",x"01A",x"021", -- 0x0300
+ x"02D",x"03B",x"055",x"072",x"0AA",x"0F0",x"181",x"250", -- 0x0308
+ x"009",x"00B",x"00D",x"00F",x"013",x"016",x"01C",x"023", -- 0x0310
+ x"030",x"03E",x"057",x"075",x"0AD",x"0F2",x"182",x"250", -- 0x0318
+ x"00A",x"00D",x"00F",x"011",x"014",x"018",x"01F",x"026", -- 0x0320
+ x"031",x"040",x"059",x"076",x"0AE",x"0F3",x"183",x"250", -- 0x0328
+ x"00D",x"00F",x"011",x"014",x"017",x"01A",x"020",x"027", -- 0x0330
+ x"034",x"042",x"05B",x"079",x"0B0",x"0F5",x"183",x"250", -- 0x0338
+ x"010",x"013",x"014",x"017",x"01A",x"01E",x"023",x"02A", -- 0x0340
+ x"037",x"045",x"05E",x"07B",x"0B2",x"0F7",x"184",x"250", -- 0x0348
+ x"014",x"016",x"018",x"01A",x"01E",x"021",x"027",x"02E", -- 0x0350
+ x"03B",x"048",x"061",x"07E",x"0B5",x"0FA",x"186",x"250", -- 0x0358
+ x"01A",x"01C",x"01F",x"020",x"023",x"027",x"02D",x"034", -- 0x0360
+ x"040",x"04E",x"067",x"084",x"0BA",x"0FE",x"188",x"250", -- 0x0368
+ x"021",x"023",x"026",x"027",x"02A",x"02E",x"034",x"03B", -- 0x0370
+ x"047",x"055",x"06E",x"08A",x"0C0",x"103",x"18C",x"250", -- 0x0378
+ x"02D",x"030",x"031",x"034",x"037",x"03B",x"040",x"047", -- 0x0380
+ x"053",x"061",x"079",x"096",x"0CA",x"10C",x"192",x"250", -- 0x0388
+ x"03B",x"03E",x"040",x"042",x"045",x"048",x"04E",x"055", -- 0x0390
+ x"061",x"06F",x"087",x"0A2",x"0D7",x"118",x"19E",x"250", -- 0x0398
+ x"055",x"057",x"059",x"05B",x"05E",x"061",x"067",x"06E", -- 0x03A0
+ x"079",x"087",x"09D",x"0B9",x"0EC",x"12C",x"1AF",x"258", -- 0x03A8
+ x"072",x"075",x"076",x"079",x"07B",x"07E",x"084",x"08A", -- 0x03B0
+ x"096",x"0A2",x"0B9",x"0D4",x"106",x"145",x"1C4",x"267", -- 0x03B8
+ x"0AA",x"0AD",x"0AE",x"0B0",x"0B2",x"0B5",x"0BA",x"0C0", -- 0x03C0
+ x"0CA",x"0D7",x"0EC",x"106",x"137",x"176",x"1F0",x"27F", -- 0x03C8
+ x"0F0",x"0F2",x"0F3",x"0F5",x"0F7",x"0FA",x"0FE",x"103", -- 0x03D0
+ x"10C",x"118",x"12C",x"145",x"176",x"1B2",x"220",x"2AE", -- 0x03D8
+ x"181",x"182",x"183",x"183",x"184",x"186",x"188",x"18C", -- 0x03E0
+ x"192",x"19E",x"1AF",x"1C4",x"1F0",x"220",x"286",x"30C", -- 0x03E8
+ x"250",x"250",x"250",x"250",x"250",x"250",x"250",x"250", -- 0x03F0
+ x"250",x"250",x"257",x"267",x"27F",x"2AE",x"30C",x"37A", -- 0x03F8
+ x"009",x"00C",x"00D",x"010",x"013",x"017",x"01D",x"024", -- 0x0400
+ x"030",x"03E",x"058",x"075",x"0AD",x"0F3",x"183",x"251", -- 0x0408
+ x"00C",x"00E",x"010",x"012",x"016",x"019",x"01F",x"026", -- 0x0410
+ x"033",x"041",x"05A",x"077",x"0AF",x"0F4",x"184",x"251", -- 0x0418
+ x"00D",x"010",x"012",x"014",x"017",x"01B",x"022",x"029", -- 0x0420
+ x"034",x"043",x"05C",x"079",x"0B1",x"0F6",x"185",x"251", -- 0x0428
+ x"010",x"012",x"014",x"017",x"01A",x"01D",x"023",x"02A", -- 0x0430
+ x"037",x"045",x"05E",x"07B",x"0B2",x"0F7",x"185",x"251", -- 0x0438
+ x"013",x"016",x"017",x"01A",x"01D",x"021",x"026",x"02D", -- 0x0440
+ x"03A",x"048",x"061",x"07E",x"0B4",x"0FA",x"186",x"251", -- 0x0448
+ x"017",x"019",x"01B",x"01D",x"021",x"024",x"02A",x"031", -- 0x0450
+ x"03E",x"04B",x"064",x"081",x"0B8",x"0FC",x"188",x"251", -- 0x0458
+ x"01D",x"01F",x"022",x"023",x"026",x"02A",x"030",x"037", -- 0x0460
+ x"043",x"051",x"06A",x"086",x"0BC",x"101",x"18A",x"251", -- 0x0468
+ x"024",x"026",x"029",x"02A",x"02D",x"031",x"037",x"03E", -- 0x0470
+ x"04A",x"058",x"070",x"08C",x"0C2",x"105",x"18E",x"251", -- 0x0478
+ x"030",x"033",x"034",x"037",x"03A",x"03E",x"043",x"04A", -- 0x0480
+ x"056",x"064",x"07B",x"098",x"0CD",x"10F",x"194",x"251", -- 0x0488
+ x"03E",x"041",x"043",x"045",x"048",x"04B",x"051",x"058", -- 0x0490
+ x"064",x"072",x"089",x"0A4",x"0D9",x"11A",x"1A0",x"251", -- 0x0498
+ x"058",x"05A",x"05C",x"05E",x"061",x"064",x"06A",x"070", -- 0x04A0
+ x"07B",x"089",x"0A0",x"0BB",x"0EE",x"12E",x"1B1",x"259", -- 0x04A8
+ x"075",x"077",x"079",x"07B",x"07E",x"081",x"086",x"08C", -- 0x04B0
+ x"098",x"0A4",x"0BB",x"0D6",x"109",x"147",x"1C6",x"269", -- 0x04B8
+ x"0AD",x"0AF",x"0B1",x"0B2",x"0B4",x"0B8",x"0BC",x"0C2", -- 0x04C0
+ x"0CD",x"0D9",x"0EE",x"109",x"139",x"178",x"1F2",x"280", -- 0x04C8
+ x"0F3",x"0F4",x"0F6",x"0F7",x"0FA",x"0FC",x"101",x"105", -- 0x04D0
+ x"10E",x"11A",x"12E",x"147",x"178",x"1B3",x"221",x"2AF", -- 0x04D8
+ x"183",x"184",x"185",x"185",x"186",x"188",x"18A",x"18E", -- 0x04E0
+ x"194",x"1A0",x"1B1",x"1C6",x"1F1",x"221",x"287",x"30D", -- 0x04E8
+ x"251",x"251",x"251",x"251",x"251",x"251",x"251",x"251", -- 0x04F0
+ x"251",x"251",x"259",x"269",x"280",x"2AF",x"30D",x"37B", -- 0x04F8
+ x"00D",x"010",x"011",x"014",x"017",x"01B",x"021",x"028", -- 0x0500
+ x"034",x"042",x"05C",x"078",x"0B0",x"0F6",x"186",x"254", -- 0x0508
+ x"010",x"012",x"014",x"016",x"01A",x"01D",x"023",x"02A", -- 0x0510
+ x"036",x"044",x"05D",x"07B",x"0B2",x"0F7",x"187",x"254", -- 0x0518
+ x"011",x"014",x"016",x"018",x"01B",x"01F",x"025",x"02C", -- 0x0520
+ x"038",x"047",x"05F",x"07C",x"0B4",x"0F9",x"187",x"254", -- 0x0528
+ x"014",x"016",x"018",x"01B",x"01E",x"021",x"027",x"02E", -- 0x0530
+ x"03A",x"048",x"061",x"07F",x"0B5",x"0FA",x"188",x"254", -- 0x0538
+ x"017",x"01A",x"01B",x"01E",x"021",x"025",x"02A",x"031", -- 0x0540
+ x"03D",x"04B",x"064",x"081",x"0B8",x"0FD",x"189",x"254", -- 0x0548
+ x"01B",x"01D",x"01F",x"021",x"025",x"028",x"02E",x"035", -- 0x0550
+ x"041",x"04E",x"067",x"084",x"0BB",x"0FF",x"18A",x"254", -- 0x0558
+ x"021",x"023",x"025",x"027",x"02A",x"02E",x"034",x"03B", -- 0x0560
+ x"047",x"055",x"06D",x"089",x"0BF",x"104",x"18D",x"254", -- 0x0568
+ x"028",x"02A",x"02C",x"02E",x"031",x"035",x"03B",x"041", -- 0x0570
+ x"04E",x"05B",x"074",x"090",x"0C6",x"108",x"191",x"254", -- 0x0578
+ x"034",x"036",x"038",x"03A",x"03D",x"041",x"047",x"04E", -- 0x0580
+ x"059",x"067",x"07E",x"09B",x"0D0",x"112",x"197",x"254", -- 0x0588
+ x"042",x"044",x"047",x"048",x"04B",x"04E",x"055",x"05B", -- 0x0590
+ x"067",x"075",x"08C",x"0A8",x"0DC",x"11D",x"1A2",x"254", -- 0x0598
+ x"05C",x"05D",x"05F",x"061",x"064",x"067",x"06D",x"074", -- 0x05A0
+ x"07E",x"08C",x"0A3",x"0BE",x"0F1",x"131",x"1B3",x"25B", -- 0x05A8
+ x"078",x"07B",x"07C",x"07F",x"081",x"084",x"089",x"090", -- 0x05B0
+ x"09B",x"0A8",x"0BE",x"0D9",x"10B",x"14A",x"1C8",x"26B", -- 0x05B8
+ x"0B0",x"0B2",x"0B4",x"0B5",x"0B8",x"0BB",x"0BF",x"0C6", -- 0x05C0
+ x"0D0",x"0DC",x"0F1",x"10B",x"13C",x"17A",x"1F4",x"282", -- 0x05C8
+ x"0F6",x"0F7",x"0F9",x"0FA",x"0FD",x"0FF",x"103",x"108", -- 0x05D0
+ x"111",x"11D",x"131",x"14A",x"17A",x"1B6",x"223",x"2B0", -- 0x05D8
+ x"186",x"187",x"187",x"188",x"189",x"18A",x"18D",x"191", -- 0x05E0
+ x"197",x"1A2",x"1B3",x"1C8",x"1F4",x"223",x"289",x"30E", -- 0x05E8
+ x"253",x"253",x"253",x"253",x"253",x"253",x"253",x"253", -- 0x05F0
+ x"253",x"253",x"25B",x"26B",x"282",x"2B0",x"30E",x"37C", -- 0x05F8
+ x"014",x"016",x"018",x"01A",x"01D",x"021",x"027",x"02E", -- 0x0600
+ x"03A",x"048",x"061",x"07E",x"0B5",x"0FA",x"18A",x"256", -- 0x0608
+ x"016",x"018",x"01B",x"01C",x"020",x"023",x"029",x"030", -- 0x0610
+ x"03C",x"04A",x"063",x"080",x"0B7",x"0FC",x"18B",x"256", -- 0x0618
+ x"018",x"01B",x"01C",x"01E",x"021",x"025",x"02B",x"032", -- 0x0620
+ x"03E",x"04C",x"065",x"081",x"0B9",x"0FD",x"18B",x"256", -- 0x0628
+ x"01A",x"01C",x"01E",x"021",x"024",x"027",x"02D",x"034", -- 0x0630
+ x"040",x"04E",x"066",x"084",x"0BA",x"0FF",x"18C",x"256", -- 0x0638
+ x"01D",x"020",x"021",x"024",x"027",x"02B",x"030",x"037", -- 0x0640
+ x"043",x"051",x"069",x"086",x"0BC",x"101",x"18D",x"256", -- 0x0648
+ x"021",x"023",x"025",x"027",x"02B",x"02E",x"034",x"03B", -- 0x0650
+ x"047",x"054",x"06D",x"089",x"0C0",x"104",x"18E",x"256", -- 0x0658
+ x"027",x"029",x"02B",x"02D",x"030",x"034",x"03A",x"041", -- 0x0660
+ x"04C",x"05A",x"073",x"08E",x"0C4",x"108",x"191",x"256", -- 0x0668
+ x"02E",x"030",x"032",x"034",x"037",x"03B",x"041",x"047", -- 0x0670
+ x"053",x"061",x"079",x"094",x"0CA",x"10D",x"194",x"256", -- 0x0678
+ x"03A",x"03C",x"03E",x"040",x"043",x"047",x"04C",x"053", -- 0x0680
+ x"05F",x"06C",x"083",x"0A0",x"0D4",x"116",x"19B",x"256", -- 0x0688
+ x"048",x"04A",x"04C",x"04E",x"051",x"054",x"05A",x"061", -- 0x0690
+ x"06C",x"07A",x"091",x"0AC",x"0E0",x"121",x"1A6",x"256", -- 0x0698
+ x"061",x"063",x"065",x"066",x"069",x"06D",x"073",x"079", -- 0x06A0
+ x"083",x"091",x"0A7",x"0C3",x"0F5",x"135",x"1B7",x"25E", -- 0x06A8
+ x"07E",x"080",x"081",x"084",x"086",x"089",x"08E",x"094", -- 0x06B0
+ x"0A0",x"0AC",x"0C3",x"0DE",x"10F",x"14E",x"1CB",x"26D", -- 0x06B8
+ x"0B5",x"0B7",x"0B9",x"0BA",x"0BC",x"0C0",x"0C4",x"0CA", -- 0x06C0
+ x"0D4",x"0E0",x"0F5",x"10F",x"13F",x"17E",x"1F6",x"284", -- 0x06C8
+ x"0FA",x"0FC",x"0FD",x"0FF",x"101",x"103",x"108",x"10C", -- 0x06D0
+ x"116",x"121",x"135",x"14E",x"17D",x"1B8",x"226",x"2B2", -- 0x06D8
+ x"18A",x"18B",x"18B",x"18C",x"18D",x"18E",x"191",x"194", -- 0x06E0
+ x"19B",x"1A6",x"1B7",x"1CB",x"1F6",x"226",x"28B",x"30F", -- 0x06E8
+ x"256",x"256",x"256",x"256",x"256",x"256",x"256",x"256", -- 0x06F0
+ x"256",x"256",x"25E",x"26D",x"284",x"2B2",x"30F",x"37D", -- 0x06F8
+ x"01B",x"01D",x"01F",x"021",x"024",x"028",x"02E",x"034", -- 0x0700
+ x"041",x"04E",x"067",x"084",x"0BB",x"100",x"18E",x"25A", -- 0x0708
+ x"01D",x"01F",x"022",x"023",x"027",x"02A",x"030",x"037", -- 0x0710
+ x"043",x"050",x"069",x"086",x"0BD",x"101",x"18F",x"25A", -- 0x0718
+ x"01F",x"022",x"023",x"025",x"028",x"02C",x"032",x"039", -- 0x0720
+ x"044",x"053",x"06B",x"087",x"0BE",x"103",x"190",x"25A", -- 0x0728
+ x"021",x"023",x"025",x"028",x"02B",x"02E",x"034",x"03B", -- 0x0730
+ x"047",x"054",x"06D",x"08A",x"0C0",x"104",x"191",x"25A", -- 0x0738
+ x"024",x"027",x"028",x"02B",x"02E",x"031",x"037",x"03E", -- 0x0740
+ x"04A",x"057",x"070",x"08C",x"0C2",x"107",x"191",x"25A", -- 0x0748
+ x"028",x"02A",x"02C",x"02E",x"031",x"034",x"03B",x"041", -- 0x0750
+ x"04D",x"05A",x"073",x"08F",x"0C5",x"109",x"193",x"25A", -- 0x0758
+ x"02E",x"030",x"032",x"034",x"037",x"03B",x"041",x"047", -- 0x0760
+ x"053",x"060",x"079",x"094",x"0CA",x"10D",x"195",x"25A", -- 0x0768
+ x"034",x"037",x"039",x"03B",x"03E",x"041",x"047",x"04D", -- 0x0770
+ x"059",x"067",x"07F",x"09A",x"0D0",x"112",x"199",x"25A", -- 0x0778
+ x"041",x"043",x"044",x"047",x"04A",x"04D",x"053",x"059", -- 0x0780
+ x"065",x"072",x"089",x"0A5",x"0D9",x"11B",x"19F",x"25A", -- 0x0788
+ x"04E",x"050",x"053",x"054",x"057",x"05A",x"060",x"067", -- 0x0790
+ x"072",x"080",x"097",x"0B2",x"0E6",x"126",x"1AA",x"25A", -- 0x0798
+ x"067",x"069",x"06B",x"06D",x"070",x"073",x"079",x"07F", -- 0x07A0
+ x"089",x"097",x"0AD",x"0C8",x"0FA",x"13A",x"1BB",x"262", -- 0x07A8
+ x"084",x"086",x"087",x"08A",x"08C",x"08F",x"094",x"09A", -- 0x07B0
+ x"0A5",x"0B2",x"0C8",x"0E3",x"114",x"152",x"1CF",x"271", -- 0x07B8
+ x"0BB",x"0BD",x"0BE",x"0C0",x"0C2",x"0C5",x"0CA",x"0D0", -- 0x07C0
+ x"0D9",x"0E6",x"0FA",x"114",x"144",x"182",x"1FA",x"287", -- 0x07C8
+ x"0FF",x"101",x"102",x"104",x"106",x"108",x"10D",x"112", -- 0x07D0
+ x"11B",x"126",x"13A",x"152",x"181",x"1BC",x"229",x"2B5", -- 0x07D8
+ x"18E",x"18F",x"190",x"191",x"191",x"193",x"195",x"199", -- 0x07E0
+ x"19F",x"1AA",x"1BB",x"1CF",x"1F9",x"229",x"28D",x"312", -- 0x07E8
+ x"25A",x"25A",x"25A",x"25A",x"25A",x"25A",x"25A",x"25A", -- 0x07F0
+ x"25A",x"25A",x"261",x"270",x"287",x"2B5",x"312",x"37F", -- 0x07F8
+ x"027",x"02A",x"02B",x"02D",x"030",x"034",x"03A",x"041", -- 0x0800
+ x"04C",x"05A",x"072",x"08E",x"0C5",x"109",x"197",x"261", -- 0x0808
+ x"02A",x"02C",x"02E",x"030",x"033",x"036",x"03C",x"043", -- 0x0810
+ x"04F",x"05C",x"074",x"090",x"0C7",x"10B",x"198",x"261", -- 0x0818
+ x"02B",x"02E",x"030",x"032",x"035",x"038",x"03E",x"045", -- 0x0820
+ x"050",x"05E",x"076",x"092",x"0C8",x"10C",x"198",x"261", -- 0x0828
+ x"02D",x"030",x"032",x"034",x"037",x"03A",x"040",x"046", -- 0x0830
+ x"052",x"060",x"078",x"094",x"0CA",x"10E",x"199",x"261", -- 0x0838
+ x"030",x"033",x"035",x"037",x"03A",x"03E",x"043",x"049", -- 0x0840
+ x"055",x"062",x"07B",x"096",x"0CC",x"110",x"19A",x"261", -- 0x0848
+ x"034",x"036",x"038",x"03A",x"03E",x"041",x"046",x"04D", -- 0x0850
+ x"059",x"065",x"07E",x"099",x"0CF",x"112",x"19B",x"261", -- 0x0858
+ x"03A",x"03C",x"03E",x"040",x"043",x"046",x"04C",x"053", -- 0x0860
+ x"05E",x"06B",x"083",x"09E",x"0D3",x"117",x"19E",x"261", -- 0x0868
+ x"041",x"043",x"045",x"046",x"049",x"04D",x"053",x"059", -- 0x0870
+ x"065",x"072",x"089",x"0A4",x"0D9",x"11B",x"1A1",x"261", -- 0x0878
+ x"04C",x"04F",x"050",x"052",x"055",x"059",x"05E",x"065", -- 0x0880
+ x"070",x"07D",x"094",x"0AF",x"0E3",x"124",x"1A7",x"261", -- 0x0888
+ x"05A",x"05C",x"05E",x"060",x"062",x"065",x"06B",x"072", -- 0x0890
+ x"07D",x"08A",x"0A1",x"0BB",x"0EF",x"12F",x"1B2",x"261", -- 0x0898
+ x"072",x"074",x"076",x"078",x"07B",x"07E",x"083",x"089", -- 0x08A0
+ x"094",x"0A1",x"0B6",x"0D1",x"103",x"142",x"1C2",x"268", -- 0x08A8
+ x"08E",x"090",x"092",x"094",x"096",x"099",x"09E",x"0A4", -- 0x08B0
+ x"0AF",x"0BB",x"0D1",x"0EB",x"11C",x"15A",x"1D6",x"277", -- 0x08B8
+ x"0C5",x"0C7",x"0C8",x"0CA",x"0CC",x"0CF",x"0D3",x"0D9", -- 0x08C0
+ x"0E3",x"0EF",x"103",x"11C",x"14B",x"189",x"200",x"28D", -- 0x08C8
+ x"109",x"10A",x"10C",x"10D",x"110",x"112",x"116",x"11B", -- 0x08D0
+ x"123",x"12F",x"142",x"15A",x"189",x"1C3",x"22F",x"2BA", -- 0x08D8
+ x"197",x"198",x"198",x"199",x"19A",x"19B",x"19E",x"1A1", -- 0x08E0
+ x"1A7",x"1B2",x"1C2",x"1D6",x"200",x"22F",x"292",x"315", -- 0x08E8
+ x"260",x"260",x"260",x"260",x"260",x"260",x"260",x"260", -- 0x08F0
+ x"260",x"260",x"268",x"276",x"28C",x"2BA",x"315",x"382", -- 0x08F8
+ x"036",x"038",x"039",x"03B",x"03E",x"042",x"048",x"04E", -- 0x0900
+ x"05A",x"067",x"07F",x"09A",x"0D0",x"114",x"1A1",x"268", -- 0x0908
+ x"038",x"03A",x"03C",x"03E",x"041",x"044",x"04A",x"050", -- 0x0910
+ x"05C",x"069",x"080",x"09C",x"0D2",x"116",x"1A1",x"268", -- 0x0918
+ x"039",x"03C",x"03E",x"040",x"043",x"046",x"04C",x"052", -- 0x0920
+ x"05D",x"06B",x"083",x"09E",x"0D4",x"117",x"1A2",x"268", -- 0x0928
+ x"03B",x"03E",x"040",x"042",x"045",x"048",x"04D",x"054", -- 0x0930
+ x"05F",x"06C",x"084",x"0A0",x"0D5",x"119",x"1A3",x"268", -- 0x0938
+ x"03E",x"041",x"043",x"045",x"048",x"04B",x"050",x"057", -- 0x0940
+ x"062",x"06F",x"087",x"0A2",x"0D7",x"11B",x"1A3",x"268", -- 0x0948
+ x"042",x"044",x"046",x"048",x"04B",x"04E",x"054",x"05A", -- 0x0950
+ x"066",x"072",x"08A",x"0A5",x"0DA",x"11D",x"1A5",x"268", -- 0x0958
+ x"048",x"04A",x"04C",x"04D",x"050",x"054",x"05A",x"060", -- 0x0960
+ x"06B",x"078",x"090",x"0AA",x"0DF",x"121",x"1A7",x"268", -- 0x0968
+ x"04E",x"050",x"052",x"054",x"057",x"05A",x"060",x"066", -- 0x0970
+ x"071",x"07E",x"095",x"0B0",x"0E4",x"126",x"1AB",x"268", -- 0x0978
+ x"05A",x"05C",x"05D",x"05F",x"062",x"066",x"06B",x"071", -- 0x0980
+ x"07C",x"089",x"09F",x"0BB",x"0EE",x"12E",x"1B0",x"268", -- 0x0988
+ x"067",x"069",x"06B",x"06C",x"06F",x"072",x"078",x"07E", -- 0x0990
+ x"089",x"096",x"0AC",x"0C6",x"0F9",x"139",x"1BB",x"268", -- 0x0998
+ x"07F",x"080",x"083",x"084",x"087",x"08A",x"090",x"095", -- 0x09A0
+ x"09F",x"0AC",x"0C1",x"0DC",x"10D",x"14C",x"1CB",x"26F", -- 0x09A8
+ x"09A",x"09C",x"09E",x"0A0",x"0A2",x"0A5",x"0AA",x"0B0", -- 0x09B0
+ x"0BB",x"0C6",x"0DC",x"0F6",x"126",x"163",x"1DE",x"27E", -- 0x09B8
+ x"0D0",x"0D2",x"0D4",x"0D5",x"0D7",x"0DA",x"0DF",x"0E4", -- 0x09C0
+ x"0EE",x"0F9",x"10D",x"126",x"154",x"192",x"207",x"293", -- 0x09C8
+ x"114",x"115",x"117",x"118",x"11A",x"11C",x"121",x"125", -- 0x09D0
+ x"12E",x"138",x"14C",x"163",x"191",x"1CA",x"235",x"2BF", -- 0x09D8
+ x"1A1",x"1A1",x"1A2",x"1A3",x"1A3",x"1A5",x"1A7",x"1AB", -- 0x09E0
+ x"1B0",x"1BB",x"1CB",x"1DE",x"207",x"235",x"298",x"31A", -- 0x09E8
+ x"268",x"268",x"268",x"268",x"268",x"268",x"268",x"268", -- 0x09F0
+ x"268",x"268",x"26F",x"27D",x"293",x"2BF",x"31A",x"386", -- 0x09F8
+ x"050",x"052",x"053",x"055",x"058",x"05B",x"061",x"067", -- 0x0A00
+ x"072",x"07E",x"096",x"0B0",x"0E5",x"128",x"1B1",x"275", -- 0x0A08
+ x"052",x"054",x"056",x"057",x"05B",x"05D",x"063",x"069", -- 0x0A10
+ x"074",x"080",x"097",x"0B2",x"0E7",x"129",x"1B2",x"275", -- 0x0A18
+ x"053",x"056",x"057",x"059",x"05C",x"05F",x"065",x"06B", -- 0x0A20
+ x"075",x"082",x"099",x"0B4",x"0E8",x"12B",x"1B3",x"275", -- 0x0A28
+ x"055",x"057",x"059",x"05B",x"05E",x"061",x"066",x"06C", -- 0x0A30
+ x"077",x"084",x"09B",x"0B6",x"0EA",x"12C",x"1B4",x"275", -- 0x0A38
+ x"058",x"05B",x"05C",x"05E",x"061",x"064",x"069",x"06F", -- 0x0A40
+ x"07A",x"086",x"09D",x"0B8",x"0EC",x"12E",x"1B4",x"275", -- 0x0A48
+ x"05B",x"05D",x"05F",x"061",x"064",x"067",x"06C",x"073", -- 0x0A50
+ x"07E",x"089",x"0A0",x"0BA",x"0EE",x"130",x"1B6",x"275", -- 0x0A58
+ x"061",x"063",x"065",x"066",x"069",x"06C",x"072",x"078", -- 0x0A60
+ x"082",x"08F",x"0A5",x"0BF",x"0F3",x"134",x"1B8",x"275", -- 0x0A68
+ x"067",x"069",x"06B",x"06C",x"06F",x"073",x"078",x"07E", -- 0x0A70
+ x"088",x"095",x"0AB",x"0C5",x"0F8",x"138",x"1BB",x"275", -- 0x0A78
+ x"072",x"074",x"075",x"077",x"07A",x"07E",x"082",x"088", -- 0x0A80
+ x"093",x"09F",x"0B5",x"0CF",x"101",x"141",x"1C0",x"275", -- 0x0A88
+ x"07E",x"080",x"082",x"084",x"086",x"089",x"08F",x"095", -- 0x0A90
+ x"09F",x"0AB",x"0C1",x"0DA",x"10C",x"14B",x"1CB",x"275", -- 0x0A98
+ x"096",x"097",x"099",x"09B",x"09D",x"0A0",x"0A5",x"0AB", -- 0x0AA0
+ x"0B5",x"0C1",x"0D5",x"0EF",x"11F",x"15D",x"1DA",x"27C", -- 0x0AA8
+ x"0B0",x"0B2",x"0B4",x"0B6",x"0B8",x"0BA",x"0BF",x"0C5", -- 0x0AB0
+ x"0CF",x"0DA",x"0EF",x"108",x"136",x"172",x"1EC",x"28A", -- 0x0AB8
+ x"0E5",x"0E7",x"0E8",x"0EA",x"0EC",x"0EE",x"0F3",x"0F8", -- 0x0AC0
+ x"101",x"10C",x"11E",x"136",x"164",x"1A0",x"213",x"29E", -- 0x0AC8
+ x"127",x"128",x"12A",x"12B",x"12D",x"12F",x"133",x"137", -- 0x0AD0
+ x"140",x"14A",x"15D",x"172",x"19F",x"1D7",x"240",x"2C8", -- 0x0AD8
+ x"1B1",x"1B2",x"1B3",x"1B4",x"1B4",x"1B6",x"1B8",x"1BB", -- 0x0AE0
+ x"1C0",x"1CB",x"1DA",x"1EC",x"212",x"240",x"2A1",x"320", -- 0x0AE8
+ x"274",x"274",x"274",x"274",x"274",x"274",x"274",x"274", -- 0x0AF0
+ x"274",x"274",x"27B",x"288",x"29D",x"2C8",x"320",x"38B", -- 0x0AF8
+ x"06D",x"06F",x"070",x"072",x"075",x"078",x"07D",x"082", -- 0x0B00
+ x"08C",x"097",x"0AE",x"0C6",x"0F9",x"13B",x"1C0",x"27D", -- 0x0B08
+ x"06F",x"071",x"073",x"074",x"077",x"079",x"07E",x"084", -- 0x0B10
+ x"08E",x"099",x"0AF",x"0C8",x"0FB",x"13C",x"1C1",x"27D", -- 0x0B18
+ x"070",x"073",x"074",x"076",x"078",x"07B",x"080",x"086", -- 0x0B20
+ x"08F",x"09B",x"0B1",x"0CA",x"0FD",x"13D",x"1C1",x"27D", -- 0x0B28
+ x"072",x"074",x"076",x"078",x"07A",x"07D",x"082",x"087", -- 0x0B30
+ x"091",x"09C",x"0B2",x"0CB",x"0FE",x"13F",x"1C2",x"27D", -- 0x0B38
+ x"075",x"077",x"078",x"07A",x"07D",x"080",x"084",x"08A", -- 0x0B40
+ x"094",x"09F",x"0B5",x"0CD",x"100",x"141",x"1C2",x"27D", -- 0x0B48
+ x"078",x"079",x"07B",x"07D",x"080",x"082",x"087",x"08D", -- 0x0B50
+ x"097",x"0A1",x"0B7",x"0D0",x"102",x"142",x"1C4",x"27D", -- 0x0B58
+ x"07D",x"07E",x"080",x"082",x"084",x"087",x"08C",x"092", -- 0x0B60
+ x"09B",x"0A6",x"0BC",x"0D4",x"106",x"146",x"1C6",x"27D", -- 0x0B68
+ x"082",x"084",x"086",x"087",x"08A",x"08D",x"092",x"097", -- 0x0B70
+ x"0A1",x"0AC",x"0C1",x"0D9",x"10B",x"14A",x"1C9",x"27D", -- 0x0B78
+ x"08C",x"08E",x"08F",x"091",x"094",x"097",x"09B",x"0A1", -- 0x0B80
+ x"0AA",x"0B5",x"0CA",x"0E3",x"113",x"151",x"1CE",x"27D", -- 0x0B88
+ x"097",x"099",x"09B",x"09C",x"09F",x"0A1",x"0A6",x"0AC", -- 0x0B90
+ x"0B5",x"0C1",x"0D5",x"0ED",x"11D",x"15B",x"1D7",x"27D", -- 0x0B98
+ x"0AE",x"0AF",x"0B1",x"0B2",x"0B5",x"0B7",x"0BC",x"0C1", -- 0x0BA0
+ x"0CA",x"0D5",x"0E7",x"100",x"12F",x"16B",x"1E5",x"283", -- 0x0BA8
+ x"0C6",x"0C8",x"0CA",x"0CB",x"0CD",x"0D0",x"0D4",x"0D9", -- 0x0BB0
+ x"0E3",x"0ED",x"100",x"118",x"145",x"17F",x"1F6",x"290", -- 0x0BB8
+ x"0F9",x"0FB",x"0FD",x"0FE",x"100",x"102",x"106",x"10B", -- 0x0BC0
+ x"113",x"11D",x"12E",x"145",x"170",x"1AB",x"21A",x"2A2", -- 0x0BC8
+ x"139",x"13A",x"13C",x"13D",x"13F",x"141",x"144",x"148", -- 0x0BD0
+ x"150",x"159",x"16B",x"17F",x"1A9",x"1DF",x"245",x"2CA", -- 0x0BD8
+ x"1C0",x"1C1",x"1C1",x"1C2",x"1C2",x"1C4",x"1C6",x"1C9", -- 0x0BE0
+ x"1CE",x"1D7",x"1E5",x"1F6",x"219",x"245",x"2A2",x"31E", -- 0x0BE8
+ x"27B",x"27B",x"27B",x"27B",x"27B",x"27B",x"27B",x"27B", -- 0x0BF0
+ x"27B",x"27B",x"282",x"28E",x"2A1",x"2CA",x"31E",x"386", -- 0x0BF8
+ x"0A5",x"0A7",x"0A8",x"0A9",x"0AB",x"0AE",x"0B2",x"0B7", -- 0x0C00
+ x"0C0",x"0C9",x"0DD",x"0F3",x"123",x"162",x"1E0",x"292", -- 0x0C08
+ x"0A7",x"0A8",x"0AA",x"0AB",x"0AE",x"0B0",x"0B4",x"0B9", -- 0x0C10
+ x"0C1",x"0CB",x"0DE",x"0F5",x"125",x"163",x"1E1",x"292", -- 0x0C18
+ x"0A8",x"0AA",x"0AB",x"0AD",x"0AF",x"0B1",x"0B6",x"0BA", -- 0x0C20
+ x"0C2",x"0CC",x"0E0",x"0F6",x"126",x"164",x"1E1",x"292", -- 0x0C28
+ x"0A9",x"0AB",x"0AD",x"0AE",x"0B0",x"0B2",x"0B7",x"0BB", -- 0x0C30
+ x"0C4",x"0CD",x"0E1",x"0F8",x"127",x"165",x"1E2",x"292", -- 0x0C38
+ x"0AB",x"0AE",x"0AF",x"0B0",x"0B2",x"0B5",x"0B9",x"0BD", -- 0x0C40
+ x"0C6",x"0CF",x"0E3",x"0F9",x"129",x"167",x"1E2",x"292", -- 0x0C48
+ x"0AE",x"0B0",x"0B1",x"0B2",x"0B5",x"0B7",x"0BB",x"0C0", -- 0x0C50
+ x"0C9",x"0D2",x"0E5",x"0FB",x"12B",x"168",x"1E3",x"292", -- 0x0C58
+ x"0B2",x"0B4",x"0B6",x"0B7",x"0B9",x"0BB",x"0C0",x"0C4", -- 0x0C60
+ x"0CC",x"0D6",x"0E9",x"0FF",x"12E",x"16C",x"1E5",x"292", -- 0x0C68
+ x"0B7",x"0B9",x"0BA",x"0BB",x"0BD",x"0C0",x"0C4",x"0C9", -- 0x0C70
+ x"0D1",x"0DB",x"0EE",x"103",x"132",x"16F",x"1E8",x"292", -- 0x0C78
+ x"0C0",x"0C1",x"0C2",x"0C4",x"0C6",x"0C9",x"0CC",x"0D1", -- 0x0C80
+ x"0D9",x"0E2",x"0F5",x"10B",x"139",x"175",x"1EC",x"292", -- 0x0C88
+ x"0C9",x"0CB",x"0CC",x"0CD",x"0CF",x"0D2",x"0D6",x"0DB", -- 0x0C90
+ x"0E2",x"0EC",x"0FF",x"114",x"142",x"17D",x"1F4",x"292", -- 0x0C98
+ x"0DD",x"0DE",x"0E0",x"0E1",x"0E3",x"0E5",x"0E9",x"0EE", -- 0x0CA0
+ x"0F5",x"0FF",x"10E",x"126",x"152",x"18B",x"1FF",x"298", -- 0x0CA8
+ x"0F3",x"0F5",x"0F6",x"0F8",x"0F9",x"0FB",x"0FF",x"103", -- 0x0CB0
+ x"10B",x"114",x"126",x"13B",x"164",x"19C",x"20E",x"2A2", -- 0x0CB8
+ x"123",x"125",x"126",x"127",x"129",x"12B",x"12E",x"132", -- 0x0CC0
+ x"139",x"142",x"150",x"164",x"18D",x"1C4",x"22E",x"2B2", -- 0x0CC8
+ x"160",x"161",x"162",x"163",x"164",x"166",x"169",x"16C", -- 0x0CD0
+ x"173",x"17A",x"18B",x"19C",x"1C2",x"1F4",x"256",x"2D5", -- 0x0CD8
+ x"1E0",x"1E1",x"1E1",x"1E2",x"1E2",x"1E3",x"1E5",x"1E8", -- 0x0CE0
+ x"1EC",x"1F4",x"1FF",x"20E",x"22B",x"256",x"2AD",x"324", -- 0x0CE8
+ x"290",x"290",x"290",x"290",x"290",x"290",x"290",x"290", -- 0x0CF0
+ x"290",x"290",x"295",x"2A0",x"2B0",x"2D5",x"324",x"388", -- 0x0CF8
+ x"0EB",x"0ED",x"0EE",x"0EF",x"0F1",x"0F3",x"0F7",x"0FB", -- 0x0D00
+ x"103",x"10B",x"11E",x"132",x"160",x"19D",x"217",x"2C2", -- 0x0D08
+ x"0ED",x"0EE",x"0F0",x"0F1",x"0F3",x"0F5",x"0F8",x"0FD", -- 0x0D10
+ x"104",x"10C",x"11F",x"134",x"162",x"19E",x"217",x"2C2", -- 0x0D18
+ x"0EE",x"0F0",x"0F1",x"0F2",x"0F4",x"0F6",x"0FA",x"0FE", -- 0x0D20
+ x"105",x"10E",x"120",x"135",x"163",x"19F",x"217",x"2C2", -- 0x0D28
+ x"0EF",x"0F1",x"0F2",x"0F3",x"0F5",x"0F7",x"0FB",x"0FF", -- 0x0D30
+ x"106",x"10F",x"121",x"136",x"164",x"1A0",x"218",x"2C2", -- 0x0D38
+ x"0F1",x"0F3",x"0F4",x"0F5",x"0F7",x"0F9",x"0FD",x"101", -- 0x0D40
+ x"108",x"111",x"123",x"137",x"165",x"1A1",x"218",x"2C2", -- 0x0D48
+ x"0F3",x"0F5",x"0F6",x"0F7",x"0F9",x"0FB",x"0FF",x"103", -- 0x0D50
+ x"10B",x"113",x"125",x"139",x"167",x"1A3",x"219",x"2C2", -- 0x0D58
+ x"0F7",x"0F8",x"0FA",x"0FB",x"0FD",x"0FF",x"103",x"107", -- 0x0D60
+ x"10E",x"116",x"128",x"13C",x"16A",x"1A6",x"21B",x"2C2", -- 0x0D68
+ x"0FB",x"0FD",x"0FE",x"0FF",x"101",x"103",x"107",x"10B", -- 0x0D70
+ x"112",x"11A",x"12C",x"140",x"16D",x"1A8",x"21D",x"2C2", -- 0x0D78
+ x"103",x"104",x"105",x"106",x"108",x"10B",x"10E",x"112", -- 0x0D80
+ x"119",x"121",x"133",x"147",x"173",x"1AE",x"221",x"2C2", -- 0x0D88
+ x"10B",x"10C",x"10E",x"10F",x"111",x"113",x"116",x"11A", -- 0x0D90
+ x"121",x"12A",x"13B",x"14F",x"17B",x"1B5",x"228",x"2C2", -- 0x0D98
+ x"11E",x"11F",x"120",x"121",x"123",x"125",x"128",x"12C", -- 0x0DA0
+ x"133",x"13B",x"149",x"15F",x"18B",x"1C1",x"232",x"2C6", -- 0x0DA8
+ x"132",x"134",x"135",x"136",x"137",x"139",x"13C",x"140", -- 0x0DB0
+ x"147",x"14F",x"15F",x"173",x"19A",x"1D0",x"23F",x"2D0", -- 0x0DB8
+ x"160",x"162",x"163",x"164",x"165",x"167",x"16A",x"16D", -- 0x0DC0
+ x"173",x"17B",x"187",x"19A",x"1C1",x"1F7",x"25C",x"2DE", -- 0x0DC8
+ x"19A",x"19B",x"19C",x"19D",x"19E",x"1A0",x"1A2",x"1A5", -- 0x0DD0
+ x"1AB",x"1B2",x"1C1",x"1D0",x"1F3",x"224",x"282",x"2FD", -- 0x0DD8
+ x"217",x"217",x"217",x"218",x"218",x"219",x"21B",x"21D", -- 0x0DE0
+ x"221",x"228",x"232",x"23F",x"259",x"282",x"2D5",x"348", -- 0x0DE8
+ x"2BE",x"2BE",x"2BE",x"2BE",x"2BE",x"2BE",x"2BE",x"2BE", -- 0x0DF0
+ x"2BE",x"2BE",x"2C3",x"2CC",x"2DA",x"2FD",x"348",x"3AA", -- 0x0DF8
+ x"17D",x"17E",x"17E",x"17F",x"181",x"183",x"185",x"188", -- 0x0E00
+ x"18E",x"194",x"1A4",x"1B5",x"1DF",x"218",x"288",x"325", -- 0x0E08
+ x"17E",x"17F",x"180",x"180",x"182",x"184",x"186",x"189", -- 0x0E10
+ x"18F",x"195",x"1A4",x"1B6",x"1E0",x"219",x"288",x"325", -- 0x0E18
+ x"17E",x"180",x"180",x"182",x"183",x"185",x"187",x"18A", -- 0x0E20
+ x"18F",x"196",x"1A5",x"1B6",x"1E0",x"219",x"289",x"325", -- 0x0E28
+ x"17F",x"180",x"182",x"183",x"184",x"185",x"188",x"18B", -- 0x0E30
+ x"190",x"197",x"1A6",x"1B7",x"1E1",x"21A",x"289",x"325", -- 0x0E38
+ x"181",x"182",x"183",x"184",x"185",x"187",x"189",x"18C", -- 0x0E40
+ x"192",x"198",x"1A7",x"1B8",x"1E2",x"21B",x"289",x"325", -- 0x0E48
+ x"183",x"184",x"185",x"185",x"187",x"188",x"18B",x"18E", -- 0x0E50
+ x"194",x"199",x"1A9",x"1BA",x"1E4",x"21C",x"28A",x"325", -- 0x0E58
+ x"185",x"186",x"187",x"188",x"189",x"18B",x"18E",x"191", -- 0x0E60
+ x"196",x"19C",x"1AB",x"1BC",x"1E6",x"21E",x"28B",x"325", -- 0x0E68
+ x"188",x"189",x"18A",x"18B",x"18C",x"18E",x"191",x"194", -- 0x0E70
+ x"199",x"19F",x"1AE",x"1BF",x"1E8",x"220",x"28D",x"325", -- 0x0E78
+ x"18E",x"18F",x"18F",x"190",x"192",x"194",x"196",x"199", -- 0x0E80
+ x"19E",x"1A4",x"1B3",x"1C4",x"1ED",x"224",x"290",x"325", -- 0x0E88
+ x"194",x"195",x"196",x"197",x"198",x"199",x"19C",x"19F", -- 0x0E90
+ x"1A4",x"1AA",x"1B9",x"1C9",x"1F2",x"229",x"295",x"325", -- 0x0E98
+ x"1A4",x"1A4",x"1A5",x"1A6",x"1A7",x"1A9",x"1AB",x"1AE", -- 0x0EA0
+ x"1B3",x"1B9",x"1C3",x"1D8",x"200",x"232",x"29C",x"328", -- 0x0EA8
+ x"1B5",x"1B6",x"1B6",x"1B7",x"1B8",x"1BA",x"1BC",x"1BF", -- 0x0EB0
+ x"1C4",x"1C9",x"1D8",x"1E8",x"20B",x"23D",x"2A5",x"32F", -- 0x0EB8
+ x"1DF",x"1E0",x"1E0",x"1E1",x"1E2",x"1E4",x"1E6",x"1E8", -- 0x0EC0
+ x"1ED",x"1F2",x"1FB",x"20B",x"22E",x"260",x"2BD",x"339", -- 0x0EC8
+ x"214",x"214",x"215",x"216",x"217",x"218",x"21A",x"21C", -- 0x0ED0
+ x"220",x"225",x"232",x"23D",x"25B",x"287",x"2DF",x"352", -- 0x0ED8
+ x"288",x"288",x"289",x"289",x"289",x"28A",x"28B",x"28D", -- 0x0EE0
+ x"290",x"295",x"29C",x"2A5",x"2B8",x"2DF",x"32B",x"396", -- 0x0EE8
+ x"320",x"320",x"320",x"320",x"320",x"320",x"320",x"320", -- 0x0EF0
+ x"320",x"320",x"324",x"32B",x"335",x"352",x"396",x"3F3", -- 0x0EF8
+ x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F00
+ x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F08
+ x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F10
+ x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F18
+ x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F20
+ x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F28
+ x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F30
+ x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F38
+ x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F40
+ x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F48
+ x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F50
+ x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F58
+ x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F60
+ x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F68
+ x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F70
+ x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F78
+ x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F80
+ x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F88
+ x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F90
+ x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F98
+ x"254",x"254",x"254",x"254",x"254",x"254",x"254",x"254", -- 0x0FA0
+ x"254",x"254",x"254",x"264",x"284",x"2AB",x"302",x"379", -- 0x0FA8
+ x"25C",x"25C",x"25C",x"25C",x"25C",x"25C",x"25C",x"25C", -- 0x0FB0
+ x"25C",x"25C",x"264",x"26C",x"284",x"2AB",x"302",x"379", -- 0x0FB8
+ x"27C",x"27C",x"27C",x"27C",x"27C",x"27C",x"27C",x"27C", -- 0x0FC0
+ x"27C",x"27C",x"27C",x"284",x"29C",x"2C3",x"30A",x"379", -- 0x0FC8
+ x"2A3",x"2A3",x"2A3",x"2A3",x"2A3",x"2A3",x"2A3",x"2A3", -- 0x0FD0
+ x"2A3",x"2A3",x"2AB",x"2AB",x"2BB",x"2DB",x"322",x"381", -- 0x0FD8
+ x"302",x"302",x"302",x"302",x"302",x"302",x"302",x"302", -- 0x0FE0
+ x"302",x"302",x"302",x"302",x"302",x"322",x"359",x"3B0", -- 0x0FE8
+ x"371",x"371",x"371",x"371",x"371",x"371",x"371",x"371", -- 0x0FF0
+ x"371",x"371",x"371",x"371",x"371",x"381",x"3B0",x"3FF" -- 0x0FF8
+ );
+
+begin
+
+ p_rom : process
+ begin
+ wait until rising_edge(CLK);
+ DATA <= ROM(to_integer(unsigned(ADDR)))(9 downto 0);
+ end process;
+end RTL;