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authorH. Peter Anvin <hpa@zytor.com>2010-10-23 22:38:35 -0700
committerH. Peter Anvin <hpa@zytor.com>2014-02-10 18:07:48 -0800
commitcc696aec5a3e44d4de7b72fa61b09d3d0fea699e (patch)
treee853cd4989ac33fbc0a696e9f39159e8d1bab437 /ym2149
parent6d2cc7b04f4d26a3c084ffdea5a9c82904e369b1 (diff)
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ym2149: use the clocked model
The latched model might be tha accurate thing for simulating a real circuit, but in an FPGA it synthesizes in a way that is almost guaranteed to glitch. Therefore, use the clocked model.
Diffstat (limited to 'ym2149')
-rw-r--r--ym2149/YM2149_volmix.vhd122
1 files changed, 61 insertions, 61 deletions
diff --git a/ym2149/YM2149_volmix.vhd b/ym2149/YM2149_volmix.vhd
index 7afcfb1..7abcfb4 100644
--- a/ym2149/YM2149_volmix.vhd
+++ b/ym2149/YM2149_volmix.vhd
@@ -178,70 +178,31 @@ begin
end process;
-- CLOCKED
- --p_waddr : process
- --begin
- ---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
- --wait until rising_edge(CLK);
-
- --if (RESET_L = '0') then
- --addr <= (others => '0');
- --else
- --if (busctrl_addr = '1') then
- --addr <= I_DA;
- --end if;
- --end if;
- --end process;
- --p_wdata : process
- --begin
- ---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
- --wait until rising_edge(CLK);
- --env_reset <= '0';
-
- --if (RESET_L = '0') then
- --reg <= (others => (others => '0'));
- --env_reset <= '1';
- --else
- --env_reset <= '0';
- --if (busctrl_we = '1') then
- --case addr(3 downto 0) is
- --when x"0" => reg(0) <= I_DA;
- --when x"1" => reg(1) <= I_DA;
- --when x"2" => reg(2) <= I_DA;
- --when x"3" => reg(3) <= I_DA;
- --when x"4" => reg(4) <= I_DA;
- --when x"5" => reg(5) <= I_DA;
- --when x"6" => reg(6) <= I_DA;
- --when x"7" => reg(7) <= I_DA;
- --when x"8" => reg(8) <= I_DA;
- --when x"9" => reg(9) <= I_DA;
- --when x"A" => reg(10) <= I_DA;
- --when x"B" => reg(11) <= I_DA;
- --when x"C" => reg(12) <= I_DA;
- --when x"D" => reg(13) <= I_DA; env_reset <= '1';
- --when x"E" => reg(14) <= I_DA;
- --when x"F" => reg(15) <= I_DA;
- --when others => null;
- --end case;
- --end if;
- --end if;
- --end process;
-
- -- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock.
- p_waddr : process(reset_l, busctrl_addr)
+ p_waddr : process
begin
-- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+ wait until rising_edge(CLK);
+
if (RESET_L = '0') then
addr <= (others => '0');
- elsif falling_edge(busctrl_addr) then -- yuk
- addr <= I_DA;
+ else
+ if (busctrl_addr = '1') then
+ addr <= I_DA;
+ end if;
end if;
end process;
-
- p_wdata : process(reset_l, busctrl_we, addr)
+ p_wdata : process
begin
+ -- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+ wait until rising_edge(CLK);
+ env_reset <= '0';
+
if (RESET_L = '0') then
reg <= (others => (others => '0'));
- elsif falling_edge(busctrl_we) then
+ env_reset <= '1';
+ else
+ env_reset <= '0';
+ if (busctrl_we = '1') then
case addr(3 downto 0) is
when x"0" => reg(0) <= I_DA;
when x"1" => reg(1) <= I_DA;
@@ -256,19 +217,58 @@ begin
when x"A" => reg(10) <= I_DA;
when x"B" => reg(11) <= I_DA;
when x"C" => reg(12) <= I_DA;
- when x"D" => reg(13) <= I_DA;
+ when x"D" => reg(13) <= I_DA; env_reset <= '1';
when x"E" => reg(14) <= I_DA;
when x"F" => reg(15) <= I_DA;
when others => null;
end case;
- end if;
-
- env_reset <= '0';
- if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then
- env_reset <= '1';
+ end if;
end if;
end process;
+ -- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock.
+ --p_waddr : process(reset_l, busctrl_addr)
+ --begin
+ ---- looks like registers are latches in real chip, but the address is caught at the end of the address state.
+ --if (RESET_L = '0') then
+ --addr <= (others => '0');
+ --elsif falling_edge(busctrl_addr) then -- yuk
+ --addr <= I_DA;
+ --end if;
+ --end process;
+
+ --p_wdata : process(reset_l, busctrl_we, addr)
+ --begin
+ --if (RESET_L = '0') then
+ --reg <= (others => (others => '0'));
+ --elsif falling_edge(busctrl_we) then
+ --case addr(3 downto 0) is
+ --when x"0" => reg(0) <= I_DA;
+ --when x"1" => reg(1) <= I_DA;
+ --when x"2" => reg(2) <= I_DA;
+ --when x"3" => reg(3) <= I_DA;
+ --when x"4" => reg(4) <= I_DA;
+ --when x"5" => reg(5) <= I_DA;
+ --when x"6" => reg(6) <= I_DA;
+ --when x"7" => reg(7) <= I_DA;
+ --when x"8" => reg(8) <= I_DA;
+ --when x"9" => reg(9) <= I_DA;
+ --when x"A" => reg(10) <= I_DA;
+ --when x"B" => reg(11) <= I_DA;
+ --when x"C" => reg(12) <= I_DA;
+ --when x"D" => reg(13) <= I_DA;
+ --when x"E" => reg(14) <= I_DA;
+ --when x"F" => reg(15) <= I_DA;
+ --when others => null;
+ --end case;
+ --end if;
+
+ --env_reset <= '0';
+ --if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then
+ --env_reset <= '1';
+ --end if;
+ --end process;
+
p_rdata : process(busctrl_re, addr, reg)
begin
O_DA <= (others => '0'); -- 'X'