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-rw-r--r--serial.v34
1 files changed, 8 insertions, 26 deletions
diff --git a/serial.v b/serial.v
index 76abceb..5cc2321 100644
--- a/serial.v
+++ b/serial.v
@@ -118,34 +118,16 @@ module serial (
end // always @ (negedge rst_n or posedge clk)
// Deglitch for the input
- reg [3:0] rx_deglitch;
reg rx_deglitched;
- reg tty_rxd_q;
- always @(negedge rst_n or posedge clk)
- if ( ~rst_n )
- begin
- rx_deglitch <= 4'b1111;
- tty_rxd_q <= 1'b1;
- end
- else
- begin
- tty_rxd_q <= tty_rxd;
- if ( tty_rxd_q )
- begin
- if ( ~&rx_deglitch )
- rx_deglitch <= rx_deglitch + 1;
- else
- rx_deglitched <= 1'b1;
- end
- else
- begin
- if ( |rx_deglitch )
- rx_deglitch <= rx_deglitch - 1;
- else
- rx_deglitched <= 1'b0;
- end // else: !if( tty_rxd_q )
- end // else: !if( ~rst_n )
+ debounce #(.width(1), .count(4)) rx_deglitch
+ (
+ .clk ( clk ),
+ .reset_n ( rst_n ),
+ .in ( tty_rxd ),
+ .out ( rx_deglitched ),
+ .strobe ( )
+ );
// Receive logic
reg [3:0] rx_bit_ctr;