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authorH. Peter Anvin <hpa@zytor.com>2009-09-10 17:03:23 -0700
committerH. Peter Anvin <hpa@zytor.com>2009-09-10 17:03:23 -0700
commit476fe646e1f462c50392fe9558d0fc9168a12246 (patch)
tree5656597057409aef3c03056f148c0f078f8489bc
parent268111c69545a7787f5eca4cec6902b7d3f8fc23 (diff)
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core: pxe: real-mode interrupt service routine
Real-mode interrupt service routine for PXE. All it does is poll the PXE stack, sets a flag, then issues EOI. It is then up to the PM stack to wake up the receive thread and process the packet receives. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r--core/pxe.inc8
-rw-r--r--core/pxeisr.inc89
-rw-r--r--core/pxelinux.asm5
3 files changed, 102 insertions, 0 deletions
diff --git a/core/pxe.inc b/core/pxe.inc
index 7471c4f0..52f31e0b 100644
--- a/core/pxe.inc
+++ b/core/pxe.inc
@@ -151,4 +151,12 @@
%define PXENV_STATUS_LOADER_UNDI_START 0xca
%define PXENV_STATUS_LOADER_BC_START 0xcb
+; UNDI ISR codes
+%define PXENV_UNDI_ISR_IN_START 1
+%define PXENV_UNDI_ISR_IN_PROCESS 2
+%define PXENV_UNDI_ISR_IN_GET_NEXT 3
+
+%define PXENV_UNDI_ISR_OUT_OURS 0
+%define PXENV_UNDI_ISR_OUT_NOT_OURS 1
+
%endif ; _PXE_INC
diff --git a/core/pxeisr.inc b/core/pxeisr.inc
new file mode 100644
index 00000000..df753687
--- /dev/null
+++ b/core/pxeisr.inc
@@ -0,0 +1,89 @@
+;
+; Process a PXE interrupt
+;
+ section .text16
+
+ global pxe_isr
+pxe_isr:
+ pusha
+ push ds
+ push es
+ push fs
+ push gs
+
+ xor ax,ax
+ mov ds,ax
+ mov es,ax
+
+ mov bx,PXENV_UNDI_ISR
+ mov di,pxenv_undi_isr_buf
+
+ mov cx,pxenv_undi_isr_buf.size/2
+ push di
+ rep stosw
+ pop di
+
+ mov byte [pxenv_undi_isr_buf.funcflag],PXENV_UNDI_ISR_IN_START
+
+ call pxenv
+ jc .notus
+
+ cmp word [pxenv_undi_isr_buf.funcflag],PXENV_UNDI_ISR_OUT_OURS
+ jne .notus
+
+ ; Its ours - set the flag for the return to PM.
+ ; We need to EOI this ourselves, so that the
+ ; leftover BC doesn't get control.
+ mov byte [pxe_irq_pending],1
+
+ mov al,[pxe_irq_vector]
+ cmp al,8
+ jae .aux_pic
+
+ add al,0x60 ; Specific EOI
+ jmp .pri_pic
+
+.aux_pic:
+ add al,0x60-8
+ out 0xA0,al ; Secondary PIC
+ mov al,0x62 ; Specific EOI, cascade interrupt
+.pri_pic:
+ out 0x20,al ; Primary PIC
+
+ pop gs
+ pop fs
+ pop es
+ pop ds
+ popa
+ iret
+
+.notus:
+ pop gs
+ pop fs
+ pop es
+ pop ds
+ popa
+ jmp 0:0
+pxe_irq_chain equ $-4
+
+ global pxe_irq_chain
+
+ section .bss16
+ alignb 4
+pxenv_undi_isr_buf:
+.status: resw 1
+.funcflag: resw 1
+.bufferlength: resw 1
+.framelen: resw 1
+.framehdrlen: resw 1
+.frame: resw 2
+.prottype: resb 1
+.pkttype: resb 1
+.size equ $-pxenv_undi_isr_buf
+
+ global pxe_irq_num
+pxe_irq_vector resb 1 ; PXE IRQ vector
+ global pxe_irq_pending
+pxe_irq_pending resb 1 ; IRQ pending flag
+
+ section .text16
diff --git a/core/pxelinux.asm b/core/pxelinux.asm
index 93ef8b4a..88d03298 100644
--- a/core/pxelinux.asm
+++ b/core/pxelinux.asm
@@ -430,6 +430,11 @@ pxe_int1a:
%endif
ret
+; -----------------------------------------------------------------------------
+; PXE modules
+; -----------------------------------------------------------------------------
+
+%include "pxeisr.inc"
; -----------------------------------------------------------------------------
; Common modules